LTC7821 datasheet(7/18 Pages) AD

7 / 18 page

LTC7060

Rev. A

For more information www.analog.com

PIN FUNCTIONS

VCC: VCC Supply. IC bias supply referred to the SGND pin.

An internal 4.5V supply is generated from the VCC supply

to bias most of the internal circuitry. A bypass capacitor

with a minimum value of 0.1uF should be tied between

this pin and the SGND pin.

BGVCC: Bottom MOSFET Driver Supply. The bottom

MOSFET gate driver is biased between this pin and the

BGRTN pin. An external capacitor should be tied between

this pin and BGRTN and placed close to the IC.

BGRTN: Bottom MOSFET Driver Return. The bottom

gate driver is biased between BGVCC and BGRTN. Kelvin

connect BGRTN to the bottom MOSFET source pin for

high noise immunity. The voltage difference between the

BGRTN pin and the SGND can be –10V to 100V.

BG: Bottom MOSFET Gate Driver Output. This pin drives

the gate of the N-channel MOSFET between BGRTN and

BGVCC.

BST: Top MOSFET Driver Supply. The top MOSFET gate

driver is biased between this pin and the SW pin. An exter-

nal capacitor should be tied between this pin and the SW

pin and placed close to the IC.

SW: Top MOSFET Driver Return. The top gate driver is

biased between BST and SW. Kelvin connect SW to the top

MOSFET source pin for high noise immunity. The voltage

difference between the SW pin and SGND can be –10V

to 100V.

TG: Top MOSFET Gate Driver Output. This pin drives the

gate of the N-channel MOSFET between SW and BST.

DT: Dead-Time Program Pin Referred to the SGND Pin.

A single resistor from this pin to SGND sets the BG/TG

low to TG/BG high propagation delay. See the operation

section for details.

PWM: Three-State Gate Driver Input Signal Referred to

the SGND Pin. The TG/BG state is determined by the volt-

age at this pin. If this pin is floating, an internal resistor

divider triggers the High-Z mode in which both BG and

TG are turned off. Trace capacitance on this pin should

be minimized.

EN: Enable Control Input Pin Referred to the SGND Pin.

A voltage on this pin above 1.2V enables the gate drivers.

The TG and BG pins are both in the low state if this pin

is logic low.

FLT: Open Drain Fault Output Pin Referred to the SGND

Pin. Open-drain output that pulls to SGND during VCC

UVLO/OVLO and floating supplies UVLO condition. The

typical pull-down resistance is 60Ω.

NC: No Internal Connection. Always keep this pin floating.

It is intentionally skipped to isolate adjacent high voltage

pins.

SGND: Chip Ground. The exposed pad must be soldered

to the PCB ground for electrical contact and for rated

thermal performance.

BLOCK DIAGRAM

BST

UVLO

LEVEL

SHIFTER

BGVCC

BGRTN

UVLO

LEVEL

SHIFTER

DRIVER

LOGIC

SHOOT-

THROUGH

PROTECTION

1.0V

3.1V

PWM

1.2V

4.5V

48k

42k

UVLO

VCC

OVLO

FLT

DELAY

SGND

7060 BD

DRIVER

–

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