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VG6640 Datasheet(PDF) 72 Page - STMicroelectronics |
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VG6640 Datasheet(HTML) 72 Page - STMicroelectronics |
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72 / 126 page  Video timing VG6640, VD6640 72/126 DocID023597 Rev 11 Figure 18. Programmable addressable region of the pixel array The host must ensure that: • the end address is greater than the start address • the x and y start addresses are restricted to even numbers only, and the x and y end addresses are restricted to odd numbers only (this is to ensure that there is always an even number of pixels readout) • the window of interest is not smaller than 264 x 264 Figure 19. Programmable frame output size y_addr_max = 979 x_addr_max = 1303 y_addr_min = 0 x_addr_min = 0 x_addr_max, y_addr_max x_addr_end, y_addr_end Addressed pixel array region x_addr_start, y_addr_start x_addr_min, y_addr_min Visible Pixels 1304 x 980 2 Embedded Data Header Lines 2 Digital ASIL Lines 2 Analogue ASIL Lines 6 Embedded Data Trailer Lines FS (CSI) FE (CSI) X_output_size FRAME BLANKING |
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