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VG6640 Datasheet(PDF) 14 Page - STMicroelectronics

Part # VG6640
Description  Automotive 1.3 megapixel high-dynamic range image sensor
PDF  126 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VG6640 Datasheet(HTML) 14 Page - STMicroelectronics

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Signal, ball assignment, pad, and wafer description
VG6640, VD6640
14/126
DocID023597 Rev 11
2
Signal, ball assignment, pad, and wafer description
2.1
Signal description
Table 4. Signal description with Im2BGA 100 balls
Pin name
Type(1)
Description
Reset
state(2)
Reference
supply
Power supplies
VCORE
PWR
1V2 power supply for the digital core (optional, 1V2 may
be generated internally using the LDO regulator)
1.2 V
VDIG
PWR
1V8 power supply for the I/O ring (and internal LDO
regulator)
1.8 V
VANA
PWR
2V8 power supply for analog blocks
2.8 V
DGND
PWR
Digital ground
1.8 V
AGND
PWR
Analog ground
VANA
Reference
VRTSF
REF
Internal reference. Must be connected by 220nF
capacitor to AGND
N/A
Clocks
EXTCLK_XTAL1
I-SCH
External clock input, or, crystal oscillator input (dependent
on state of EXTCLK_EN pin)
N/A
XTAL2
O
Crystal oscillator output
N/A
CSI2 interface
DP_DL1, DN_DL1
O
CSI2 data lane 1, positive and negative
HI_Z
VCORE
DP_DL2, DN_DL2
O
CSI2 data lane 2, positive and negative
HI_Z
VCORE
DP_CL, DN_CL
O
CSI2 clock, positive and negative
HI_Z
VCORE
Parallel (ITU) interface
DOUT[11:0]
O
ITU Data lines
LO
VDIG
PIXCLK
O
ITU Pixel Clock
LO
VDIG
HSYNC
O
ITU Horizontal Sync
LO
VDIG
VSYNC
O
ITU Vertical Sync
LO
VDIG
Control interface
XSHUTDOWN
I-SCH
Internal 1V2 LDO enable (HI enables the regulator)
VDIG
RESET_N
I-SCH-
PU20
Master reset for digital core
VDIG
EXTCLK_EN
I-PD5
External clock enable input
LO
VDIG
SDA
I/O
I2C-style data
VDIG



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