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AD4680 Datasheet(PDF) 5 Page - Analog Devices

Part # AD4680
Description  Differential Inputs, 1 MSPS/500 kSPS, Dual Simultaneous Sampling SAR ADCs
PDF  29 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4680 Datasheet(HTML) 5 Page - Analog Devices

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Data Sheet
AD4680/AD4681
Rev. 0 | Page 5 of 29
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, and TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
Description
tCYC
Time between conversions
1
μs
AD4680
2
μs
AD4681
tSCLKED
190
ns
CS falling edge to first SCLK falling edge
tSCLK
25
ns
SCLK period
tSCLKH
10
ns
SCLK high time
tSCLKL
10
ns
SCLK low time
tCSH
10
ns
CS pulse width
tQUIET
Interface quiet time prior to conversion
500
ns
1500
ns
tSDOEN
CS low to SDOA and SDOB/ALERT enabled
6
ns
VLOGIC ≥ 2.25 V
8
ns
1.65 V ≤ VLOGIC < 2.25 V
tSDOH
2
ns
SCLK rising edge to SDOA and SDOB/ALERT hold time
tSDOS
SCLK rising edge to SDOA and SDOB/ALERT setup time
6
ns
VLOGIC ≥ 2.25 V
8
ns
1.65 V ≤ VLOGIC < 2.25 V
tSDOT
45
ns
CS rising edge to SDOA and SDOB/ALERT high impedance
tSDIS
1
ns
SDI setup time prior to SCLK falling edge
tSDIH
1
ns
SDI hold time after SCLK falling edge
tSCLKCS
0
ns
SCLK rising edge to CS rising edge
tCONVERT
190
ns
Conversion time
tACQUIRE
Acquire time
810
ns
AD4680
1800
ns
AD4681
tRESET
Valid time to start conversion after software reset (see Figure 37)
250
ns
Valid time to start conversion after soft reset
800
ns
Valid time to start conversion after hard reset
tPOWERUP
Supply active to conversion
5
ms
First conversion allowed
11
ms
Settled to within 1% with internal reference
5
ms
Settled to within 1% with external reference
tREGWRITE
5
ms
Supply active to register read write access allowed
tSTARTUP
Exiting shutdown mode to conversion
11
ms
Settled to within 1% with internal reference
10
μs
Settled to within 1% with external reference
tALERTS
200
ns
Time from CS to ALERT indication (see Figure 36)
tALERTC
12
ns
Time from CS to ALERT clear (see Figure 36)



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