AD4680 datasheet(23/29 Pages) AD

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Data Sheet

AD4680/AD4681

Rev. 0 | Page 23 of 29

READING FROM DEVICE REGISTERS

All registers in the device can be read over the serial interface. A

followed by an additional SPI command that can be either a

valid command or no operation command (NOP). The format

for a read command is shown in Table 14. Bit D15 must be set

to 0 to select a read command. Bits[D14:D12] contain the

ignored.

WRITING TO DEVICE REGISTERS

All read/write registers in the AD4680/AD4681 can be written

to over the serial interface. The length of an SPI write access is

determined by the CRC write function. An SPI access is 16-bit

if CRC write is disabled and is 24-bit when CRC write is

enabled. The format for a write command is shown in Table 14.

Bit D15 must be set to 1 to select a write command.

Bits[D14:D12] contain the register address, and the subsequent

12 bits, Bits[D11:D0], contain the data to be written to the

selected register.

CRC

The AD4680/AD4681 have CRC checksum modes that can be

used to improve interface robustness by detecting errors in data

transmissions. The CRC feature is independently selectable for

SPI interface reads and SPI interface writes. For example, the

CRC function for SPI writes can be enabled to prevent

unexpected changes to the device configuration but disabled on

SPI reads, therefore maintaining a higher throughput rate. The

CRC feature is controlled by the programming of the CRC_W

and CRC_R bits in the CONFIGURATION1 register.

CRC Read

If enabled, a CRC is appended to the conversion result or

calculated in the conversion result for ADC A and ADC B and

is output on SDOA. A CRC is also calculated and appended to

The CRC read function can be used in 2-wire SPI mode, 1-wire

SPI mode, and resolution boost mode.

CRC Write

To enable the CRC write function, the CRC_W bit in the

CONFIGURATION1 register must be set to 1. To set the

CRC_W bit to 1 to enable the CRC feature, the request frame

must have a valid CRC appended to the frame.

After the CRC feature is enabled, all register write requests are

ignored unless accompanied by a valid CRC command, requiring a

valid CRC to both enable and disable the CRC write feature.

CRC Polynomial

For CRC checksum calculations, the following polynomial is

always used: x8 + x2 + x + 1.

The following is an example of how to generate the checksum

on a conversion read. The 16-bit data conversion result of the

two channels are combined to produce a 32-bit data. The

8 MSBs of the 32-bit data are inverted and then left shifted by

eight bits to create a number ending in eight Logic 0s. The

polynomial is aligned such that the MSB is adjacent to the

leftmost Logic 1 of the data. An exclusive OR (XOR) function is

applied to the data to produce a new, shorter number. The

polynomial is again aligned such that the MSB is adjacent to the

leftmost Logic 1 of the new result, and the procedure is

repeated. This process repeats until the original data is reduced

to a value less than the polynomial, which is the 8-bit

checksum. The polynomial for this example is 100000111.

Let the original data of two channels be 0xAAAA and 0x5555,

that is, 1010 1010 1010 1010 and 0101 0101 0101 0101. The data

of the two channels is appended including eight zeros on the

right, and then becomes 1010 1010 1010 1010 0101 0101 0101

0101 0000 0000.

Table 12 shows the CRC calculation of 16-bit, 2-channel data

for the AD4680/AD4681. In the final XOR operation, the

reduced data is less than the polynomial. Therefore, the

remainder is the CRC for the assumed data.

SDI

SDOA

RESULT S0

REG 1DATA

REG 2DATA

RESULT S3

INVALID

RESULT S0

INVALID

READ REG 1

READ REG 2

NOP

RESULT S3

SDOB/ALERT

Figure 43. Register Read

SDI

RESULT S0

RESULT S1

RESULT S2

INVALID

WRITE REG 1

WRITE REG 2

NOP

SDOA

SDOB/ALERT

Figure 44. Register Write

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