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MCP39F511A Datasheet(PDF) 4 Page - Microchip Technology |
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MCP39F511A Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 68 page ![]() MCP39F511A DS20006044A-page 4 2018 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † DVDD .................................................................. -0.3 to +4.5V AVDD .................................................................. -0.3 to +4.0V Digital inputs and outputs w.r.t. AGND...............-0.3V to +4.0V Analog Inputs (I+,I-,V+,V-) w.r.t. AGND ...................-2V to +2V VREF input w.r.t. AGND ........................ ....-0.6V to AVDD +0.6V Maximum Current out of DGND pin..............................300 mA Maximum Current into DVDD pin.................................250 mA Maximum Output Current Sunk by Digital IO ................25 mA Maximum Current Sourced by Digital IO.......................25 mA Storage temperature .....................................-65°C to +150°C Ambient temperature with power applied......-40°C to +125°C Soldering temperature of leads (10 seconds) .............+300°C ESD on the analog inputs (HBM,MM) .................4.0 kV, 200V ESD on all other pins (HBM,MM) ........................4.0 kV, 200V † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1.1 Specifications TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions Power Measurement Active Power (Note 1) P — ±0.1 — % 4000:1 Dynamic range on current channel (Note 2) Reactive Power (Note 1) Q — ±0.1 — % 4000:1 Dynamic range on current channel (Note 2) Apparent Power (Note 1) S — ±0.1 — % 4000:1 Dynamic range on current channel (Note 2) Current RMS (Note 1) IRMS — ±0.1 — % 4000:1 Dynamic range on current channel (Note 2) Voltage RMS (Note 1) VRMS — ±0.1 — % 4000:1 (DC mode), 20:1 (AC mode) Dynamic range on voltage channel (Note 2, 8) Power Factor (Note 1) —±0.1 — % Line Frequency (Note 1) LF — ±0.1 — % Calibration, Calculation and Event Detection Times Auto-Calibration Time tCAL — 2N x(1/fLINE) —ms Note 3 Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. 2: Specification by design and characterization; not production tested. 3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL =80 ms for 50 Hz line. 4: Applies to Voltage Sag and Voltage Surge events only. 5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. 6: VIN =1.2 VPP =424 mVRMS @ 50/60 Hz. This parameter is established by characterization and is not 100% tested. 7: Variation applies to internal clock and UART only. All calculated output quantities can be temperature compensated to the performance listed in the respective specification. 8: The internal ADC clock frequency is affected by the amplitude of the AC signal applied on the voltage channel, decreasing the overall accuracy if the amplitude is low. In DC mode, the internal ADC clock frequency is constant. |
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