MCP39F511A datasheet(6/68 Pages) MICROCHIP

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MCP39F511A

DS20006044A-page 6

 2018 Microchip Technology Inc.

Absolute Input Voltage

VIN

DGND -0.3

—

DVDD +0.3

Recommended

Impedance of

Analog Voltage Source

RIN

——

2.5



Integral Nonlinearity

INL

—±1

±2

LSb

Differential Nonlinearity

DNL

—±1

±1.5

LSb

Gain Error

GERR

—±1

±3

LSb

Offset Error

EOFF

—±1

±2

LSb

Temperature

Measurement Rate

—

fLINE/2N

—sps

Note 7

Clock and Timings

UART Baud Rate

UDB

1.2

9.6

115.2

kbps

See Section 3.2 for

protocol details

Master Clock

and Crystal Frequency

fMCLK

-2%

+2%

MHz

Capacitive Loading

on OSCO pin

COSC2

—

When an external clock is

used to drive the device

Internal Oscillator

Tolerance

fINT_OSC

—

-40 to +85°C only

(Note 7)

Internal Voltage Reference

Internal Voltage

Reference Tolerance

VREF

-2%

1.2

+2%

VREFEXT =0,

TA =+25°C only

Temperature Coefficient

TCVREF

—7

—

ppm/°C TA = -40°C to +125°C,

VREFEXT =0

Output Impedance

ZOUTVREF

—2

—



VREFEXT =0

Current, VREF

AIDDVREF

—25

—

AVREFEXT =0

SHUTDOWN<1:0>=11

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications:

Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V, TA = -40°C to +125°C,

MCLK = 4 MHz, PGA GAIN = 1.

Characteristic

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Note

Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4

line cycles.

Specification by design and characterization; not production tested.

N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL =80 ms for

50 Hz line.

Applies to Voltage Sag and Voltage Surge events only.

Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance

Curves”

for typical performance.

VIN =1.2 VPP =424 mVRMS @ 50/60 Hz. This parameter is established by characterization and is not 100% tested.

Variation applies to internal clock and UART only. All calculated output quantities can be temperature compensated to

the performance listed in the respective specification.

The internal ADC clock frequency is affected by the amplitude of the AC signal applied on the voltage channel,

decreasing the overall accuracy if the amplitude is low. In DC mode, the internal ADC clock frequency is constant.

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