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SN74LS228 Datasheet(PDF) 8 Page - Texas Instruments |
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SN74LS228 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 10 page ![]() SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10–8 APPLICATION INFORMATION 5 V LDCK D0 D1 D2 D3 LDCK 10 ns IR IRE OE OR UNCK ORE D0 D1 D2 D3 Q0 Q1 Q2 Q3 LDCK 10 ns IR IRE OE OR UNCK ORE Q0 Q1 Q2 Q3 5 V 5 V D0 D1 D2 D3 IR IRE OE OR UNCK ORE Q0 Q1 Q2 Q3 5 V LDCK D0 D1 D2 D3 LDCK IR IRE OE OR UNCK ORE D0 D1 D2 D3 Q0 Q1 Q2 Q3 LDCK IR IRE OE OR UNCK ORE Q0 Q1 Q2 Q3 5 V 5 V D0 D1 D2 D3 IR IRE OE OR UNCK ORE Q0 Q1 Q2 Q3 5 V 5 V LDCK D0 D1 D2 D3 LDCK IR IRE OE OR UNCK ORE D0 D1 D2 D3 Q0 Q1 Q2 Q3 LDCK IR IRE OE OR UNCK ORE Q0 Q1 Q2 Q3 5 V 5 V D0 D1 D2 D3 IR IRE OE OR UNCK ORE Q0 Q1 Q2 Q3 5 V 5 V LDCK D0 D1 D2 D3 LDCK IR IRE OE OR UNCK ORE D0 D1 D2 D3 Q0 Q1 Q2 Q3 LDCK IR IRE OE OR UNCK ORE Q0 Q1 Q2 Q3 5 V 5 V D0 D1 D2 D3 IR IRE OE OR UNCK ORE Q0 Q1 Q2 Q3 5 V 5 V Open Open Open Open Open Open 5 V 5 V CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR LDCK IR OE UNCK OR 10 ns ≡ Noninverting delay ≥ 10 ns (e.g., two stages of ’LS04), two places. Figure 1. 48-Word by 16-Bit Expansion Using ’LS227 |
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