SN74LS228

16

× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

WITH OPEN-COLLECTOR OUTPUTS

SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993

POST OFFICE BOX 655303

Copyright

10–1

Outputs

Printed-Circuit-Board Layout

description

This 64-bit memory is a low-power Schottky memory array organized as 16 words by 4 bits. It can be expanded

in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and

m is the number of packages in the horizontal array), however some external gating is required (see Figure 1).

For longer words using the SN74LS228, the IR signals of the first-rank packages and OR signals of the last-rank

packages must be ANDed for proper synchronization.

A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array

at independent data rates. These FIFOs are designed to process data at rates from 0 to 10 MHz in a bit-parallel

format, word by word.

Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a

low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked

in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on

the data residing in memory. When the memory is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the input-ready (IR) and output-ready (OR) flags that indicate not-full

and not-empty conditions. IR is high only when the memory is not full and the LDCK is low. OR is high only when

the memory is not empty and UNCK is high.

A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low

to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to

the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR

and OR outputs.

The SN74LS228 is characterized for operation from 0

°C to 70°C.

OE

IR

LDCK

D0

D1

D2

D3

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

UNCK

OR

Q0

Q1

Q2

Q3

CLR

N PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.