MCP6C04 datasheet(33/54 Pages) MICROCHIP

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DS20006179A-page 33

MCP6C04

4.1.3.2

DC Current Errors

Figure 4-3 shows the resistors and currents that

change the DC bias point. The input bias currents (IBP,

IBM and IBR), together with a circuit’s external input

resistances, give an DC error (see Equation 1-2).

FIGURE 4-3:

DC Bias Resistors and

Currents.

RSH is set by the design requirements, given the load

current (IL). For most applications, RSH would be

between 100 µΩ and 1Ω.

The DC input offset error due to the input currents is:

VOS_IR =VDM –ILRSH

=IBM(RSH +RWIM)–IBPRWIP

Since these currents do not correlate, minimize the

magnitude of each resistance. IBPRIP will dominate in

many designs.

RWR modifies the gain error and the DC output offset

error (VOUT changes IBR):

EQUATION 4-5:

4.1.4

AC PERFORMANCE

The bandwidth of these parts (fBW) is set internally to

either 500 kHz (GDM = 20 or 50) or 390 kHz

(GDM = 100).

The large signal bandwidth is close to the small signal

bandwidth. The slew rate (SR) has little effect on VOUT

(a benefit of our Current-mode architecture).

The bandwidth at the maximum output swing is called

the Full Power Bandwidth (fFPBW). It is limited by the

Slew Rate (SR) for many amplifiers, but is close to fBW

for these parts. This is a benefit of the Current-mode

architecture these parts have.

These parts are compensated to have a stable

response. For instance, step response overshoot is

low. To be stable, VREF must see a low impedance and

VOUT must have a low capacitive load (see Figure 4-6

to compensate large capacitive loads).

In this data sheet, the AC CMRR is measured at VIP.

This is accurate, since VDM is relatively small.

4.1.5

TEMPERATURE PERFORMANCE

The input offset voltage’s temperature drift is detailed in

Equation 1-6. Other temperature responses are shown

in Section 1.3, Specifications and Section 2.0

“Typical Performance Curves”.

Since there are three power supply pins (VIP, VDD and

VSS), and VIP reaches 52V, power and temperature rise

calculations are important.

The power dissipated is calculated as follows (IOUT is

positive when it flows out of the VOUT pin):

EQUATION 4-6:

Now we can estimate the junction temperature of the

device (see Table 1-4):

EQUATION 4-7:

4.1.6

NOISE PERFORMANCE

This part is designed to have low input noise voltage

density at lower frequencies. The offset correction

(Section 4.2.2, Chopping Action) modulates high

frequency white noise down to DC; it also modulates

low frequency 1/f noise to higher frequencies.

The measured input noise voltage density is shown in

Figure 2-47. That figure also shows Integrated Input

Noise Voltage (Eni, in units of VRMS) between 0 Hz and

f (between 0.1 Hz and 100 kHz).

The Input Noise Voltage Density (eni) changes with

VDM. However, that relationship is a weak one.

IBR

VDD

VSS

MCP6C04

VOUT

RWR

VHV

Load

RSH

IBM

IBP

RWIM

RWIP

ΔVREF

IBRRWR

–

ΔgE

RWRGDM

–

() RF RG

()

⁄

≈

VOUT

VREF ΔVREF

() GDMVDM 1gE ΔgE

()

≈

PTOT

PDD PBP POUT

Where:

IOUT =(VOUT –VL)/RL

PDD =(VDD –VSS)IDD

PBP =(VIP –VSS)IBP

POUT =(VDD –VOUT)IOUT, IOUT ≥0A

=(VSS –VOUT)IOUT, IOUT <0A

TA PTOTθJA

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