HD49330AF/AHF

Rev.1.0, Apr.05.2004, page 13 of 19

Serial Interface Specifications

Resister 2

Resister 0

Resister 4 to 7

Test Mode (can not be used)

Resister 3

Resister 1

Low

Low to High

Low to High

SHA-fsel [0] (LSB)

SHA-fsel [1] (MSB)

SHSW-fsel [0] (LSB)

Low: Normal operation mode

High: Sleep mode

SLP

Low: Normal operation mode

High: Standby mode

STBY

Low: CDSIN input mode

High: YIN input mode

CSEL

Low: CDSIN input mode

High: YIN input mode

YSEL

Timing Specifications

Table 10 Serial Data Function List

SCK

CS

SDATA

DI

00

DI

01

DI

02

DI

03

DI

04

DI

05

DI

06

DI

07

DI

08

DI

09

DI

10

DI

11

DI

12

DI

13

DI

14

DI

15

Latches SDATA

at SCK rising edge

Data is determined

at CS rising edge

Figure 8 Serial Interface Timing Specifications

DI 00 (LSB)

DI 01

Low

Low

High

Low

Low

Low

Low

High

High

Low

High

High

DI 02

X

DI 03

DI 04

DI 05

DI 06

DI 07

DI 08

DI 09

DI 10

DI 11

DI 12

DI 13

DI 14

DI 15 (MSB)

PGA gain setting *

5

PGA gain setting (LSB) *

5

PGA gain setting *

5

PGA gain setting *

5

PGA gain setting *

5

PGA gain setting *

5

PGA gain setting *

5

PGA gain setting *

5

PGA gain setting *

5

PGA gain setting (MSB) *

5

Cannot be used. *

8

Cannot be used. *

8

Cannot be used. *

8

Cannot be used. *

8

Cannot be used. *

8

Cannot be used. *

8

Low

Low

Low

High

High

Low

50 ns

50 ns

50 ns



Min







5 MHz

Max

Notes: 1.

2.

3.

4.

5.

6.

7.

8.

2 byte continuous communications.

SDATA is latched at SCK rising edge.

Insert 16 clocks of SCK while CS is low.

Data is invalid if data transmission is aborted during transmission.

The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.

STBY: Reference voltage generator circuit is in the operating state.

SLP: All circuits are in the sleep state.

This bit is used for the IC testing, and cannot be used by the user.

Please do not set up in addition to "ALL Low".

This bit is used for the IC testing, and cannot be used by the user.

It is set to the state on the right of a column when RESET bit is set to low. The register

3 should transmit by setup on the right of a column.

Output mode setting (LINV)

Output mode setting (MINV)

Output mode setting (TEST0)

SHAMP

frequency

character-

istics

switching

SHSW-fsel [1]

SHSW-fsel [2]

SHSW-fsel [3] (MSB)

SHSW

frequency

character-

istics

switching

HGstop-Hsel [1]

HGain-Nsel [0]

Clamp-level [3]

Clamp-level [2]

Clamp-level [1]

Clamp-level [0] (LSB)

Clamp-level [4] (MSB)

HGstop-Hsel [0]

HGain-Nsel [1]

Low: Normal mode

High: Low power mode

LoPwr

SPinv,

SPSIG/SPBLK/PBLK inversion

OBPinv, OBP inversion

Low: Reset mode

High: Normal operation mode

RESET

High-speed

lead-in

cancellation

time

High-speed

lead-in

gain

multiplication

YC-Bias off

Output mode setting (TEST1)

Cannot be used. *

7

All low

Cannot be used. *

7

All low

Cannot be used. *

7

All low

Cannot be used. *

7

All low

Average4, 4 lines average