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DAC8581IPWR Datasheet(PDF) 5 Page - Texas Instruments |
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DAC8581IPWR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 14 page ![]() www.ti.com TIMING REQUIREMENTS (1) SCLK tLead t wsck t wsck t r t f -- Don’t Care BIT-14 BIT-13, …, 1 BIT-15 (MSB) BIT-0 SDIN t hi tsu DAC Updated tUPDAC 1st 2nd 15th 16th ttd CS t sck t WAIT TYPICAL CHARACTERISTICS −20 −15 −10 −5 0 5 10 15 20 0 8192 16384 24576 32768 40960 49152 57344 65536 Input Code −0.5 −0.25 0 0.25 0.5 0 8192 16384 24576 32768 40960 49152 57344 65536 Input Code DAC8581 SLAS481A – AUGUST 2005 – REVISED AUGUST 2005 PARAMETER MIN MAX UNIT tsck SCLK period 20 ns twsck SCLK high or low time 10 ns tLead Delay from falling CS to first rising SCLK 20 ns ttd CS High between two active Periods 20 ns tsu Data setup time (Input) 5 ns thi Data hold time (input) 5 ns tr Rise time 30 ns tf Fall time 30 ns twait Delay from 16th falling edge of SCLK to CS low 100 ns tUPDAC Delay from 16th falling edge of SCLK to DAC output 1 µs VDD High to CS Low (power-up delay) 100 µs (1) Assured by design. Not production tested. Figure 1. DAC8581 Timing Diagram LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs vs INPUT CODE INPUT CODE Figure 2. Figure 3. 5 |
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