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THEORY OF OPERATION

Supply Pins

Reference Input Voltage

Output Voltage

DAC8581

SLAS481A – AUGUST 2005 – REVISED AUGUST 2005

DAC8581 uses proprietary, monotonic, high-speed resistor string architecture. The 16-bit input data is coded in

twos complement, MSB-first format and transmitted using a 3-wire serial interface. The serial interface sends the

input data to the DAC latch. The digital data is then decoded to select a tap voltage of the resistor string. The

resistor string output is sent to a high-performance output amplifier. The output buffer has rail-to-rail (

±5 V) swing

capability on a 600-

Ω, 200-pF load. The resistor string DAC architecture provides exceptional differential linearity

and temperature stability whereas the output buffer provides fast-settling, low-glitch, and exceptionally low

idle-channel noise. The DAC8581 settles within 1

µs for large input signals. Exceptionally low glitch (0.5 nV-s) is

attainable

for

small-signal,

code-to-code

output

changes.

Resistor

string

architecture

also

provides

code-independent power consumption and code-independent settling time. The DAC8581 resistor string needs

an external reference voltage to set the output voltage range of the DAC. To aid fast settling, VREF input is

internally buffered.

DAC8581 uses

±5-V analog power supplies (AV

digital ground pins (AGND and DGND) are also provided. For low-noise operation, analog and digital power and

ground pins should be separated. Sufficient bypass capacitors, at least 1

µF, should be placed between AV

DD

paths. The digital input pins should not exceed the ground potential during power up. During power up, AGND

All digital pins must be kept at ground potential before power up.

capacitor 0.1

µF or less is recommended depending on the load-driving capability of the voltage reference. To

recommended to set the DAC8581 output range to

±3.3 V and ±4.096 V, respectively.

The input data format is in twos-complement format as shown in Table 1. DAC8581 uses a high-performance,

rail-to-rail output buffer capable of driving a 600-

Ω, 200-pF load with fast 0.65-µs settling. The buffer has

exceptional noise performance (20 nV/

√Hz) and fast slew rate (35 V/µs). The small-signal settling time is under

300 ns, allowing update rates up to 3 MSPS. Loads of 50

Ω or 75 Ω could be driven as long as output current

does not exceed

±25 mA continuously. Long cables, up to 1 nF in capacitance, can be driven without the use of

external buffers. To aid stability under large capacitive loads (>1 nF), a small series resistor can be used at the

output.

Table 1. Data Format

DIGITAL CODE

DAC OUTPUT

BINARY

HEX

+Vref

0111111111111111

7FFF

+Vref/2

0100000000000000

4FFF

0

0000000000000000

0000

–Vref/2

1011111111111111

BFFF

–Vref

1000000000000000

8000

9