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STANDARD APPLICATION

R

1%

0.05 W

SET

PTH12040W

2

4

6

12

15

9

1

11

14

19

20

18

V

I

V

O

V

O

V

I

C

560 F

(Required)

I

m

C1

330 F

(Required)

O

m

C2

330 F

(Required)

O

m

7

8

UVLO Prog

Inhibit

+Sense

-Sense

GND

Margin

Up

Margin

Down

Track

V Adj

O

17

Track

Margin Up

Margin Down

Inhibit

L

O

A

D

+Sense

-Sense

GND

GND

GND

3 5 10 13

16

PTH12040W

SLTS237A–DECEMBER 2004–REVISED OCTOBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

A.

values.)

B.

C.

ORDERING INFORMATION

PTH12040W

VOLTAGE

CODE

DESCRIPTION

Pb – free and RoHS

Compatible

AH

Horizontal T/H

Yes

EVF

0.8 V – 5.5 V (Adjust)

AS

No

EVG

AZ

Yes

EVG

(1) Add T to end of part number for tape and reel on SMD packages only.

(2) Reference the applicable package reference drawing for the dimensions and PC board layout.

(3) Standardoption specifies 63/37, Sn/Pb pin solder material.

(4) Pb – free option specifies Sn/Ag pin solder material.

2