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VT82C686B Datasheet(PDF) 27 Page - List of Unclassifed Manufacturers

Part # VT82C686B
Description  PCI Super-I/O Integrated Peripheral Controller
PDF  128 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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VT82C686B Datasheet(HTML) 27 Page - List of Unclassifed Manufacturers

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VT82C686B
Revision 1.71 June 9, 2000
-21-
Pinouts
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Internal Keyboard Controller
Signal Name
Pin #
I/O
Signal Description
MSCK / IRQ1
D5
IO / I
MultiFunction Pin (Internal mouse controller enabled by Rx5A[1])
Rx5A[1]=1 Mouse Clock. From internal mouse controller.
Rx5A[1]=0 Interrupt Request 1. Interrupt input 1.
MSDT / IRQ12
C5
IO / I
MultiFunction Pin (Internal mouse controller enabled by Rx5A[1])
Rx5A[1]=1 Mouse Data. From internal mouse controller.
Rx5A[1]=0 Interrupt Request 12. Interrupt input 12.
KBCK / A20GATE
E5
IO / I
MultiFunction Pin (Internal keyboard controller enabled by Rx5A[0])
Rx5A[0]=1 Keyboard Clock. From internal keyboard controller
Rx5A[0]=0 Gate A20. Input from external keyboard controller.
KBDT / KBRC
A5
IO / I
MultiFunction Pin (Internal keyboard controller enabled by Rx5A[0])
Rx5A[0]=1 Keyboard Data. From internal keyboard controller.
Rx5A[0]=0 Keyboard Reset. From external keyboard controller (KBC)
for CPURST# generation
KBCS# / ROMCS# / strap
C1
O / O / I
Keyboard Chip Select (Rx5A[0]=0). To external keyboard controller chip.
Power-Up Configuration Strap (Sampled At Reset):
4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1
KBIN[6-3] / SD[7-4]
W4,
Y4,
V3,
W3
I / IO
Keyboard Inputs 6-3.
Sampled at reset on SD[7-4] and latched into
Rx5A[7-4].
Chip Selects
Signal Name
Pin #
I/O
Signal Description
ROMCS# / KBCS# / strap
C1
O
ROM Chip Select (Rx5A[0]=1). Chip Select to the BIOS ROM.
Power-Up Configuration Strap (Sampled At Reset):
4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1
PCS0# / GPO12 / XDIR
T5
O
Programmable Chip Select 0 (Rx76[1] = 1 and Rx8B[0] = 1). Asserted
during I/O cycles to programmable read or write ISA I/O port ranges.
Addressed devices drive data to the SD pins (XDIR is disabled and the X-
Bus is not implemented). See also Rx59[3] and Rx77[2].
MCCS# / GPO13 / SOE#
U5
O
Microcontroller Chip Select (Rx76[3] = 1, Rx76[4] = 0, Rx77[0] = 1).
Asserted during read or write accesses to I/O ports 62h or 66h.
MCCS# / GPI11 / GPO11
/ GPIOD
U8
O
Microcontroller Chip Select (Alternate Pin) (Rx76[4] = 0 selects MCCS#
on pin U8, Rx76[4] = 1 selects MCCS# on pin U5). Rx76[3] = 1 enables
MCCS# output on the selected pin.



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