VT82C686B
Revision 1.71 June 9, 2000
-68-
Function 1 Registers - Enhanced IDE Controller
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Function 1 Registers - Enhanced IDE Controller
This Enhanced IDE controller interface is fully compatible
with the SFF 8038i v.1.0 specification. There are two sets of
software accessible registers -- PCI configuration registers and
Bus Master IDE I/O registers. The PCI configuration registers
are located in the function 1 PCI configuration space of the
VT82C686B. The Bus Master IDE I/O registers are defined in
the SFF8038i v1.0 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID (1106h=VIA) ................................RO
Offset 3-2 - Device ID (0571h=IDE Controller) ...............RO
Offset 5-4 - Command.......................................................RW
15-10 Reserved
........................................ always reads 0
9
Fast Back to Back Cycles ....... default = 0 (disabled)
8
SERR# Enable......................... default = 0 (disabled)
7
Address Stepping ...................... fixed at 1 (enabled)
A value of 1 provides additional address decode time
to IDE devices.
6
Parity Error Response ............ default = 0 (disabled)
5
VGA Palette Snoop ....................fixed at 0 (disabled)
4
Memory Write & Invalidate .....fixed at 0 (disabled)
3
Special Cycles .............................fixed at 0 (disabled)
2Bus Master ............................. default = 0 (disabled)
S/G operation can be issued only when the “Bus
Master” bit is enabled.
1
Memory Space............................fixed at 0 (disabled)
0
I/O Space
............................. default = 0 (disabled)
When the “I/O Space” bit is disabled, the device will
not respond to any I/O addresses for both compatible
and native mode.
Offset 7-6 - Status ...............................................................RO
15
Detected Parity Error ........................ always reads 0
14
Signalled System Error...................... always reads 0
13
Received Master Abort...................... always reads 0
12
Received Target Abort ...................... always reads 0
11
Signalled Target Abort ...................... always reads 0
10-9 DEVSEL# Timing ............always reads 01 (medium)
8
Data Parity Detected.......................... always reads 0
7
Fast Back to Back .............................. always reads 1
6-0
Reserved
........................................ always reads 0
Offset 8 - Revision ID (06) .................................................RO
0-7
Revision Code for IDE Controller Logic Block
Offset 9 - Programming Interface ................................... RW
7
Master IDE Capability........... fixed at 1 (Supported)
6-4
Reserved
........................................ always reads 0
3
Programmable Indicator - Secondary ...... fixed at 1
Supports both modes (may be set to either mode by
writing bit-2)
2
Reserved
........................................ always reads 0
1
Programmable Indicator - Primary .......... fixed at 1
Supports both modes (may be set to either mode by
writing bit-0)
0
Reserved
........................................ always reads 0
Compatibility Mode (fixed IRQs and I/O addresses):
Command Block
Control Block
Channel
Registers
Registers
IRQ
Pri
1F0-1F7
3F6
14
Sec
170-177
376
15
Native PCI Mode (registers are programmable in I/O space)
Command Block
Control Block
Channel
Registers
Registers
Pri
BA @offset 10h
BA @offset 14h
Sec
BA @offset 18h
BA @offset 1Ch
Command register blocks are 8 bytes of I/O space
Control registers are 4 bytes of I/O space (only byte 2 is used)
Offset A - Sub Class Code (01h=IDE Controller) ........... RO
Offset B - Base Class Code (01h=Mass Storage Ctrlr) ... RO
Offset C – Cache Line Size (00h)...................................... RO
Offset D - Latency Timer (Default=0)............................. RW
Offset E - Header Type (00h)............................................ RO
Offset F - BIST (00h) ......................................................... RO
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