GS9020 datasheet(19/30 Pages) ETC1

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6.0 RESET

Setting the RESET input pin LOW re-initializes the internal

control circuitry including returning all HOST interface

programming values to their original default values.

internal power-on-reset cell is also present in the device so

that device initialization occurs on power-up.

Figure 16a

illustrates the reset circuitry.

The internal power-on reset

circuit of the GS9020 is sensitive to the rise time of the

power supply, hence an external power on reset chip or

board level reset line is strongly recommended.

When

using this technique, the user must ensure that a minimum

pulse width of 100ns is present on the reset line.

In applications where a board-level reset is not available, a

circuit similar to figure 16b can be used to ensure correct

reset on power-up. The RESET pin will typically take 1.4ms

to reach 2.5V on power up, but can take longer for power

supplies with slower rise times. A bleed resistor such as

the one shown (20k) will assist the capacitor to discharge

once power is removed. The user should allow the

capacitor to discharge to at least 0.5V before power is

reapplied, to permit a full internal reset. The time taken by

the RESET pin to reach 0.5V on power down, is dependent

upon the fall time of the power supply.

LOGIC OPR

HOST BIT

RESET

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