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Fig. 14c HOSTIF Parallel Port READ/WRITE Cycles
Fig. 15 Host Interface READ/WRITE Timing
Fig. 16a Reset Circuitry
Fig. 16b Acceptable external reset circuit when a master reset is
not available
WRITE CYCLE
READ CYCLE
P[7:0]
A/D
R/W
CS
ADDRESS
ADDRESS
DATA
DATA
DATA IN
t0
t1
t2
t3
t4
VALID TIME TO READ/WRITE
EDH INFORMATION TO/FROM GS9020
FIELD 0
FIELD 1
FIELD 2
DOUT[9:0]
E
D
H
F0
E
D
H
F1
t0
2 LINES
SDI/SDI
EDH F0
EDH F1
INTERNAL
POWER on
RESET CELL
INTERNAL
RESET
SIGNAL
tMAX = 25µs
tRESET
RESET
PIN
Manual
Reset
Switch
(Optional)
RESET
VDD
0V
0V
5V
5V
VDD
RESET
~1.4 mS
t
t
2k
1uF
20k