ADAQ7980 datasheet(32/38 Pages) AD

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Data Sheet

ADAQ4001

APPLICATIONS INFORMATION

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Rev. 0 | 32 of 38

3-WIRE CS MODE WITH THE BUSY INDICATOR

To connect a single ADAQ4001 device to an SPI-compatible digital

host that has an interrupt input (IRQ), use 3-wire CS mode with the

busy indicator.

Figure 60 shows the connection diagram, and Figure 61 shows the

corresponding timing diagram.

When SDI is connected to VIO, a rising edge on CNV initiates

a conversion, selects the CS mode, and forces SDO to high impe-

dance. SDO is maintained in high impedance until the completion

of the conversion irrespective of the state of CNV. Prior to the

minimum conversion time, CNV can select other SPI devices, such

as analog multiplexers. However, CNV must be returned low before

the minimum conversion time elapses and then held low for the

maximum possible conversion time to guarantee the generation of

the busy signal indicator.

When the conversion completes, SDO goes from high impedance

to low impedance. With a pull-up resistor of 1 kΩ on the SDO line,

this transition can be used as an interrupt signal to initiate the data

reading controlled by the digital host. The ADAQ4001 then enters

the acquisition phase and powers down. The data bits are then

clocked out, MSB first, by subsequent SCK falling edges. The data

is valid on both SCK edges. Although the rising edge can capture

the data, a digital host using the SCK falling edge allows a faster

reading rate, provided that the digital host has an acceptable hold

time. After the optional 17th SCK falling edge or when CNV goes

high (whichever occurs first), SDO returns to high impedance.

If multiple ADAQ4001 devices are selected at the same time, the

SDO output pin handles this contention without damage or induced

latch-up. Meanwhile, it is recommended to keep this contention as

short as possible to limit extra power dissipation.

There must not be any digital activity on the SCK during the

conversion.

Figure 60. 3-Wire CS Mode with the Busy Indicator Connection Diagram (SDI High)

Figure 61. 3-Wire CS Mode with the Busy Indicator Serial Interface Timing Diagram (SDI High)

ADAQ7980 Datasheet(PDF) 32 Page - Analog Devices