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ADAQ7980 Datasheet(PDF) 3 Page - Analog Devices

Part # ADAQ7980
Description  16-Bit, 2 MSPS, 關Module Data Acquisition Solution
PDF  38 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAQ7980 Datasheet(HTML) 3 Page - Analog Devices

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Data Sheet
ADAQ4001
SPECIFICATIONS
analog.com
Rev. 0 | 3 of 38
VDD = 1.8 V ± 5%, VS+ = 5.5 V ± 5%, VS− = 0 V, VIO = 1.7 V to 5.5 V, reference voltage (VREF) = 5 V, sampling frequency (fS) = 2 MSPS, all
specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled, unless otherwise noted. ADC driver
configured in single-ended to differential configuration and normal mode, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bit
ANALOG INPUTS
IN+, IN−, R1K1+, R1K1−, R1K+, and R1K−
Input Impedance (ZIN)
Single-ended to differential configuration
G = 0.454, input voltage (VIN) = 22 V p-p
1.3
kΩ
G = 0.909, VIN = 11 V p-p
1.44
kΩ
G = 1, VIN = 10 V p-p
1.33
kΩ
G = 1.9, VIN = 5.2 V p-p
778
Ω
Fully differential configuration
G = 0.454 and G = 0.909, VIN = 22 V p-p and
11 V p-p
1.1
kΩ
G = 1, VIN = 10 V p-p
1
kΩ
G = 1.9, VIN = 5.2 V p-p
523
Ω
Differential Input Voltage Ranges1
G = 0.454, VIN = 22 V p-p
−2.2 × VREF
+2.2 × VREF
V
G = 0.909, VIN = 11 V p-p
−1.1 × VREF
+1.1 × VREF
V
G = 1, VIN = 10 V p-p
−VREF
+VREF
V
G = 1.9, VIN = 5.2 V p-p
−0.526 × VREF
+0.526 × VREF
V
Input Capacitance
IN+ and IN−
15
pF
THROUGHPUT
Complete Cycle
500
ns
Conversion Time
290
320
ns
Acquisition Phase2
290
ns
Throughput Rate3
0
2
MSPS
Transient Response4
40
µs
DC ACCURACY
Single-ended to differential configuration
No Missing Codes
16
Bits
Integral Nonlinearity Error (INL)
All gains, VS− = −1 V
−11.9
±4.6
+11.9
ppm
−0.78
±0.3
+0.78
LSB5
Differential Nonlinearity Error (DNL)
All gains, VS− = −1 V
−9.56
±3.8
+9.56
ppm
−0.63
±0.25
+0.63
LSB5
Transition Noise
G = 0.454
57
μV
G = 0.909
63.2
μV
G = 1
60.9
μV
G = 1.9
61.3
μV
Gain Error
All gains
−0.05
±0.005
+0.05
% FS
Gain Error Drift
All gains
−3
±0.5
+3
ppm/°C
Offset Error
G = 0.454
−1
±0.1
+1
mV
G = 0.909, G = 1
−0.9
±0.06
+0.9
mV
G = 1.9
−1.5
±0.01
+1.5
mV
Offset Error Drift
G = 0.454
−8
+0.7
+8
ppm/°C
G = 0.909 and G = 1
−10
+1.6
+10
ppm/°C
G = 1.9
−15
+2.6
+15
ppm/°C
Common-Mode Rejection Ratio (CMRR)
Fully differential configuration, all gains
90
dB
Power Supply Rejection Ratio (PSRR)
Positive
VDD = 1.71 V to 1.89 V
72
dB
VS+ = 5.225 V to 5.775 V, VS− = 0 V
110
dB



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