AD9375 datasheet(16/61 Pages) AD

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AD9375

Data Sheet

Rev. 0 | Page 16 of 61

Pin No.

Type1

Mnemonic

Description

B7, B8

I/O

RX_EXTLO−, RX_EXTLO+

Differential Rx External LO Input/Output. If used for the

external LO, the input frequency must be 2× the desired

carrier frequency. Do not connect if these pins are unused.

B14

VDDA_3P3

Supply Voltage for GPIO_3P3_x.

C1, C2, C13, D1, D5, D12 to D14,

E1, E14, F1, F14

I/O

GPIO_3P3_0 to GPIO_3P3_11

General-Purpose Inputs and Outputs Referenced to 3.3 V

Supply. See Figure 4 to match the ball location to the

GPIO_3P3_x signal name. Some GPIO_3P3_x pins can also

function as auxiliary DAC outputs.

VSNRX_VCO_LDO

Sniffer VCO LDO 1.1 V Output. Bypass this pin with a 1 µF

capacitor.

VDDA_SNRXVCO

1.3 V Supply Input for Sniffer VCO Low Dropout (LDO)

Regulator.

VDDA_RXLO

1.3 V Supply for the Rx Synthesizer LO Generator. This pin

is sensitive to aggressors.

VDDA_RXVCO

1.3 V Supply Input for Receiver VCO LDO Regulator.

VRX_VCO_LDO

Receiver VCO LDO 1.1 V Output. Bypass this pin with a 1 µF

capacitor.

C11

AUXADC_1

Auxiliary ADC 1 Input.

C12

AUXADC_2

Auxiliary ADC 2 Input.

C14

N/A

RBIAS

Bias Resistor Connection. This pin generates an internal

current based on an external 1% resistor. Connect a

14.3 kΩ resistor between this pin and ground (VSSA).

D2, E2

SNRXC−, SNRXC+

Differential Input for Sniffer Receiver Input C. If these pins are

unused, connect to VSSA with a short or with a 1 kΩ resistor.

D3, E3

SNRXB−, SNRXB+

Differential Input for Sniffer Receiver Input B. If these pins are

unused, connect to VSSA with a short or with a 1 kΩ resistor.

D4, E4

SNRXA−, SNRXA+

Differential Input for Sniffer Receiver Input A. If these pins are

unused, connect to VSSA with a short or with a 1 kΩ resistor.

D10

VDDA_1P8

1.8 V Tx Supply.

D11

AUXADC_3

Auxiliary ADC 3 Input.

VDDA_BB

1.3 V Supply Input for ADCs, DACs, and Auxiliary ADCs.

E7, E8

DEV_CLK_IN+, DEV_CLK_IN−

Device Clock Differential Input.

E11, E12

I/O

TX_EXTLO−, TX_EXTLO+

Differential Tx External LO Input/Output. If these pins are

used for the external LO, the input frequency must be 2×

the desired carrier frequency. Do not connect if these pins

are unused.

E13

AUXADC_0

Auxiliary ADC 0 Input.

VDDA_RXTX

1.3 V Supply Input for Tx/Rx Baseband Circuits,

Transimpedance Amplifier (TIA), Tx Transconductance (G

m),

Baseband Filters, and Auxiliary DACs.

F11

VDDA_TXVCO

1.3 V Supply Input for Transmitter VCO LDO Regulator.

F12

VDDA_TXLO

1.3 V Supply for the Tx Synthesizer LO Generator. This pin is

sensitive to aggressors.

F13

VTX_VCO_LDO

Transmitter VCO LDO 1.1 V Output. Bypass this pin with a

1 µF capacitor.

VDDA_CALPLL

1.3 V Supply Input for Calibration PLL Circuits. Use a

separate trace on the PCB back to a common supply point.

VDDA_CLKSYNTH

1.3 V Clock Synthesizer Supply Input. This pin is sensitive

to aggressors.

VDDA_SNRXSYNTH

1.3 V Sniffer Rx Synthesizer Supply Input. This pin is

sensitive to aggressors.

VDDA_TXSYNTH

1.3 V Tx Synthesizer Supply Input. This pin is sensitive to

aggressors.

VDDA_RXSYNTH

1.3 V Rx Synthesizer Supply Input. This pin is sensitive to

aggressors.

H1, J1

TX2−, TX2+

Differential Output for Transmitter 2.

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