MCP3461 datasheet(29/108 Pages) MICROCHIP

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DS20006180D-page 29

MCP3461/2/4

4.13

MCP3461/2/4 Delta-Sigma

Architecture

A Delta-Sigma ADC is an oversampling converter that

incorporates a built-in modulator, which digitizes the

quantity of charge integrated by the modulator loop.

The quantizer is the block that performs the Analog-

to-Digital conversion. The quantizer is typically 1-bit or

a simple comparator that helps to maintain the linearity

performance of the ADC (the DAC structure, is in this

case, inherently linear).

Multibit quantizers help to lower the quantization error

(the error fed back in the loop can be very large with 1-bit

quantizers) without changing the order of the modulator

or the OSR that leads to better SNR figures. However,

typically, the linearity of such architectures is more

difficult to achieve since the DAC is no more simple to

realize and its linearity limits the THD of such ADC.

The modulator 5-level quantizer is a Flash ADC

composed of four comparators arranged with equally

spaced thresholds and a thermometer coding. The

device also includes proprietary 5-level DAC architecture

that is inherently linear for improved THD figures.

4.14

Power Supply Rejection Ratio

(PSRR)

This is the ratio between a change in the power supply

voltage and the ADC output codes. It measures the

influence of the power supply voltage on the ADC outputs.

The PSRR specification can be DC (the power supply

is taking multiple DC values) or AC (the power supply

is a sine wave at a certain frequency with a certain

Common-mode). In AC, the amplitude of the sine wave

represents the change in the power supply.

EQUATION 4-10:

Where VOUT is the equivalent input voltage that the

output code translates to with the ADC transfer function.

4.15

Common-Mode Rejection Ratio

(CMRR)

This is the ratio between a change in the

Common-mode input voltage and the change in ADC

output codes. It measures the influence of the

Common-mode input voltage on the ADC outputs.

The CMRR specification can be DC (Common-mode

input voltage is taking multiple DC values) or AC (the

Common-mode input voltage is a sine wave at a certain

frequency with a certain Common-mode). In AC, the

amplitude of the sine wave represents the change in

the input Common-mode voltage. CMRR is defined in

Equation 4-11.

EQUATION 4-11:

Where VINCOM = (VIN+ + VIN-)/2 is the Common-mode

input voltage and VOUT is the equivalent input voltage

that the output code translates to with the ADC transfer

function.

4.16

Digital Pins’ Output Current

Consumption

The digital current consumption, shown in the Electrical

Characteristics table, does not take into account the

current consumption generated by the digital output

pins and the charge of their capacitive loading. The

specification is intended with all output pins left floating

and no communication.

In order to estimate the additional current consumption

due to the output pins, refer to Equation 4-2. This equa-

tion specifies the amount of additional current due to

each pin when its output is connected to a Cload capac-

itance, with respect to DGND and submitted to an output

signal toggling at an fout frequency.

If a typical 10 MHz SPI frequency is used, with a 30 pF

load and DVDD = 3.3V, the SDO output generates an

additional maximum current consumption of 500 µA

(the maximum toggling frequency of SDO is 5 MHz

here, since fSCK = 10 MHz and this maximum happens

when the ADC output code is a succession of ‘1’s and

‘0’s). The Cload value includes internal digital output

driver capacitance, but this one can generally be

neglected with respect to the external loading

capacitance.

EQUATION 4-12:

PSRR dB



V

OUT

AV

-------------------





log

CMRR dB



V

OUT

V

INCOM

------------------------





log

DIDDSPI

Cload DVDD



fout



Where:

Cload = Capacitance on the Output Pin

DVDD = Digital Supply Voltage

fout = Output Frequency on the Output Pin

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