MCP3461 datasheet(62/108 Pages) MICROCHIP

62 / 108 page

MCP3461/2/4

DS20006180D-page 62

 2019-2021 Microchip Technology Inc.

These three interrupt status bits are independent of the

two other interrupt mechanisms (IRQ pin and IRQ

fully clocked. This enables the polling on the STATUS

byte as a possible interrupt management solution

without requiring to connect the IRQ pin in the system.

All status bit values are latched together just after the

device address has been correctly recognized by the

chip. Any interrupt happening after the two first status

bits have been clocked out will appear on the STATUS

byte of the next communication sequence.

Figure 6-3

represents

the

beginning

each

communication with both COMMAND and STATUS

bytes depicted. After the STATUS byte is propagated,

the SDO pin will be placed in high-impedance for Fast

commands or Write commands and will transfer data

bytes for Read commands as long as the CS pin stays

logic low.

FIGURE 6-3:

SPI Communication Start (COMMAND on SDI and STATUS on SDO) in Cases of a

Device Address Match and Not Matched.

Don’t Care

SCK

SDI

SDO

High-Z

Device Latches SDI on Rising Edge

SPI Mode 0,0

SPI Mode 1,1

Device Latches SDO on Falling Edge

Device

Address

Command

Type

Device

Address ACK

Interrupts

Status

High-Z

Device Address

Matches CMD[7:6]

High-Z

SDO

Device Address

does not Match

CMD[7:6]

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