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PCM1820 Datasheet(PDF) 7 Page - Texas Instruments |
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PCM1820 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 41 page ![]() 7.5 Electrical Characteristics (continued) at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Gain drift(4) Across temperature range -40°C to 125°C 40.5 ppm/°C Interchannel phase mismatch 1-kHz sinusoidal signal 0.02 Degrees Phase drift(5) 1-kHz sinusoidal signal, across temperature range -40°C to 125°C 0.0005 Degrees/°C PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 102 dB PCM1820: CMRR Common-mode rejection ratio Differential microphone input selected, 100-mVPP, 1-kHz signal on both pins and measure level at output 45 dB PCM1821: CMRR Common-mode rejection ratio Differential microphone input selected, 100-mVPP, 1-kHz signal on both pins and measure level at output 60 dB DIGITAL I/O VIL Low-level digital input logic voltage threshold All digital pins except FMT0, IOVDD 1.8-V operation –0.3 0.30 × IOVDD V All digital pins except FMT0, IOVDD 3.3-V operation –0.3 0.8 FMT0 Pin –0.3 0.8 V VIH High-level digital input logic voltage threshold All digital pins except FMT0, IOVDD 1.8-V operation 0.7 × IOVDD IOVDD + 0.3 V All digital pins except FMT0, IOVDD 3.3-V operation 2.1 IOVDD + 0.3 FMT0 Pin 2.1 AVDD + 0.3 V VOL Low-level digital output voltage All digital pins, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V All digital pins, IOL = –2 mA, IOVDD 3.3-V operation 0.4 VOH High-level digital output voltage All digital pins, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V All digital pins, IOH = 2 mA, IOVDD 3.3-V operation 2.4 IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA IIL Input logic-low leakage for digital inputs All digital pins, input = 0 V –5 0.1 5 µA CIN Input capacitance for digital inputs All digital pins 5 pF RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ TYPICAL SUPPLY CURRENT CONSUMPTION IAVDD Current consumption with all Clocks disabled AVDD = 3.3 V, internal AREG 0.5 mA IIOVDD All external clocks stopped, IOVDD = 3.3 V 0.5 µA IIOVDD All external clocks stopped, IOVDD = 1.8 V 0.3 IAVDD Current consumption with ADC 2-channel operating at fS 16-kHz, BCLK = 256 × fS and DRE disabled AVDD = 3.3 V, internal AREG 11.9 mA IIOVDD IOVDD = 3.3 V 0.05 IIOVDD IOVDD = 1.8 V 0.02 IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, BCLK = 256 × fS and DRE disabled AVDD = 3.3 V, internal AREG 12.9 mA IIOVDD IOVDD = 3.3 V 0.1 IIOVDD IOVDD = 1.8 V 0.05 IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, BCLK = 256 × fS and DRE enabled AVDD = 3.3 V, internal AREG 14 mA IIOVDD IOVDD = 3.3 V 0.1 IIOVDD IOVDD = 1.8 V 0.05 (1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. (2) All performance measurements done with a 20-kHz, low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. (3) For best distortion performance, use input AC-coupling capacitors with a low-voltage-coefficient. www.ti.com PCM1820, PCM1821 SBASA61A – DECEMBER 2020 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: PCM1820 PCM1821 |
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