PCMD3140IRTER datasheet(6/106 Pages) TI

6 / 106 page

6.5 Electrical Characteristics (continued)

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, PDMCLKx = 64 × fS, 32-bit audio

data, BCLK = 256 × fS, TDM slave mode, and PLL on (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output data sample rate

Programmable

7.35

768

kHz

Output data sample word

length

Programmable

Bits

Digital high-pass filter cutoff

frequency

First-order IIR filter with programmable coefficients,

–3-dB point (default setting)

MICROPHONE BIAS

MICBIAS noise

BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor

between MICBIAS and AVSS

2.1

µVRMS

MICBIAS voltage

MICBIAS programmed to VREF and VREF programmed

to either 2.75 V, 2.5 V, or 1.375 V

VREF

MICBIAS voltage

MICBIAS programmed to VREF × 1.096 and VREF

programmed to either 2.75 V, 2.5 V, or 1.375 V

VREF ×

1.096

MICBIAS voltage

Bypass to AVDD with 5-mA load

AVDD – 0.2

MICBIAS current drive

MICBIAS load regulation

MICBIAS programmed to either VREF or VREF × 1.096,

measured up to max load

0.6

MICBIAS overcurrent

protection threshold

6.1

DIGITAL I/O

VIL

Low-level digital input logic

voltage threshold

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2,

SDA and SCL, IOVDD 1.8-V operation

–0.3

0.35 ×

IOVDD

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2,

SDA and SCL, IOVDD 3.3-V operation

–0.3

0.8

VIH

High-level digital input logic

voltage threshold

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2,

SDA and SCL, IOVDD 1.8-V operation

0.65 ×

IOVDD

IOVDD + 0.3

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2,

SDA and SCL, IOVDD 3.3-V operation

IOVDD + 0.3

VOL

Low-level digital output

voltage

All digital pins except PDMCLK_GPO1, SDA and SCL,

IOL = –2 mA, IOVDD 1.8-V operation

0.45

All digital pins except PDMCLK_GPO1, SDA and SCL,

IOL = –2 mA, IOVDD 3.3-V operation

0.4

VOH

High-level digital output

voltage

All digital pins except PDMCLK_GPO1, SDA and SCL,

IOH = 2 mA, IOVDD 1.8-V operation

IOVDD –

0.45

All digital pins except PDMCLK_GPO1, SDA and SCL,

IOH = 2 mA, IOVDD 3.3-V operation

2.4

VIL(I2C)

Low-level digital input logic

voltage threshold

SDA and SCL

–0.5

0.3 x IOVDD

VIH(I2C)

High-level digital input logic

voltage threshold

SDA and SCL

0.7 x IOVDD

IOVDD + 0.5

VOL1(I2C)

Low-level digital output

voltage

SDA, IOL(I2C) = –3 mA, IOVDD > 2 V

0.4

VOL2(I2C)

Low-level digital output

voltage

SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V

0.2 x IOVDD

IOL(I2C)

Low-level digital output

current

SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode

SDA, VOL(I2C) = 0.4 V, fast-mode plus

IIH

Input logic-high leakage for

digital inputs

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2

pins,

input = IOVDD

–5

0.1

µA

IIL

Input logic-low leakage for

digital inputs

All digital pins except PDMDIN1_GPI1, PDMDIN2_GPI2

pins,

input = 0 V

–5

0.1

µA

VIL(GPIx)

Low-level digital input logic

voltage threshold

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

1.8-V operation

–0.3

0.35 × AVDD

PDMDIN1_GPI1, PDMDIN2_GPI2 digital pins, AVDD

3.3-V operation

–0.3

0.8

PCMD3140

SBASA64A – DECEMBER 2020 – REVISED JUNE 2021

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