PCMD3140IRTER datasheet(93/106 Pages) TI

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8.2.1.1 Design Requirements

The supply decoupling capacitors used must be ceramic with low ESR. Table 8-1 lists the design parameters for

this application.

Table 8-1. Design Parameters

KEY PARAMETER

SPECIFICATION

AVDD

3.3 V

AVDD supply current consumption

10 mA (PLL on, four-channel recording, fS = 48 kHz, PDMCLKx = 64 × fS)

IOVDD

1.8 V or 3.3 V

8.2.1.2 Detailed Design Procedure

This section describes the necessary steps to configure the PCMD3140 for this specific application. The

following steps provide a sequence of items that must be executed in the time between powering the device

up and reading data from the device or transitioning from one mode to another mode of operation.

1. Apply power to the device:

a. Power-up the IOVDD and AVDD power supplies

b. Wait for at least 1 ms to allow the device to initialize the internal registers initialization

c. The device now goes into sleep shutdown mode (low-power mode < 10 µA)

2. Transition from sleep mode to active mode whenever required for the recording operation:

a. Wake up the device by writing to P0_R2 to disable sleep mode

b. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence

c. Override the default configuration registers or programmable coefficients value as required (this step is

optional)

d. Configure channel 1 to channel 2 (CHx_INSRC) for the digital microphone as the input source for

recording

e. Configure GPO1 (GPO1_CFG) and GPIO1 (GPIO1_CFG) as the PDMCLK output

Configure GPIx (GPI1x_CFG) as PDMDINx

g. Enable all desired input channels by writing to P0_R115

h. Enable all desired audio serial interface output channels by writing to P0_R116

Power-up the PDM converter and PLL by writing to P0_R117

Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

This specific step can be done at any point in the sequence after step a.

See the Phase-Locked Loop (PLL) and Clock Generation section for supported sample rates and the

BCLK to FSYNC ratio.

k. The device recording data is now sent to the host processor using the TDM audio serial data bus

3. Transition from active mode to sleep mode (again) as required in the system for low-power operation:

a. Enter sleep mode by writing to P0_R2 to enable sleep mode

b. Wait at least 6 ms (when FSYNC = 48 kHz) for the volume to ramp down and for all blocks to power

down

c. Read P0_R119 to check the device shutdown and sleep mode status

d. If the device P0_R119_D7 status bit is 1'b1 then stop FSYNC and BCLK in the system

e. The device now goes into sleep mode (low-power mode < 10 µA) and retains all register values

4. Transition from sleep mode to active mode (again) as required for the recording operation:

a. Wake up the device by writing to P0_R2 to disable sleep mode

b. Wait at least 1 ms to allow the device to complete the internal wake-up sequence

c. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

d. The device recording data are now sent to the host processor using the TDM audio serial data bus

5. Repeat step 3 and step 4 as required for mode transitions and step 2 to step 4 for configuration changes.

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PCMD3140

SBASA64A – DECEMBER 2020 – REVISED JUNE 2021

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PCMD3140IRTER Datasheet(PDF) 93 Page - Texas Instruments

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