EDSTRG44PLCC datasheet(42/78 Pages) TI

42 / 78 page

GLOSSARY/SYMBOLS, TERMS, AND DEFINITIONS

1–34

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OCF:

Opcode Fetch. Goes low at the beginning of a memory read operation that fetches the first byte of an instruc-

tion. It then resumes its high level at the end of the opcode fetch(es).

offset:

A signed value that is added to the base operand to give the final address

opcode:

Operation code. The first byte of the machine code that describes to the CPU the type of operation and

combination of operands. Some TMS370 instructions use 16-bit opcodes.

operand:

The part of an instruction that tells the programmer where the CPU will fetch or store data

one-time programmable (OTP) read-only memory:

a read-only memory that, after being manufactured, can

have the data content of each memory cell altered once. Also referred to as OTP.

Output Enable:

A control input that, when true, permits data to appear at the memory output, and when false,

causes the output to assume a high-impedance state. (See also chip select.)

PACT:

Programmable acquisition and control timer module. A timer coprocessor module for the TMS370 microcon-

troller family.

PDIP:

Plastic Dual In-Line Package

peripheral file (PF):

The 128 or 256 bytes of memory, starting at 1000h, that contain the registers that control the

on-board peripherals and system configuration

peripheral-file frames:

A set of sixteen contiguous peripheral file registers, usually related by function

PLCC:

Plastic Leaded Chip Carrier

PPM:

Pulse-position modulation. A serial signal in which the information is contained in the frequency of a signal

with a constant-pulse width. By using the timer-compare features, a TMS370 device can output a PPM signal with

a constant duty cycle without any program intervention.

prescaler:

A circuit that slows the rate of a clocking source to the counter. The timer 1 prescaler can slow the clock-

ing source by a factor of 4, 16, 64, or 256.

privilege mode:

A mode immediately following reset in which the program can alter the privileged registers and

bits. Once the privilege mode is disabled, these registers cannot be changed before another reset. This mode

does not affect the EEPROM or the watchdog registers.

program:

Typically associated with EPROM and OTP memories, the procedure whereby logical 0s (or 1s) are

stored into various desired locations in a previously erased device

program counter (PC):

A CPU register that identifies the current statement in the program

prototyping device:

A device used before mask-ROM devices are available that has identical functions, pinout,

size, and timings to those of the actual device. Programmable memory such as EEPROM or EPROM is used in

place of the masked ROM.

PSDIP:

Plastic Shrink Dual In-Line Package

pulse accumulation:

A timer 1 or timer 2 mode that keeps a cumulative count of SYSCLK pulses gated by the

T1EVT or T2EVT signal

PWM:

Pulse-width modulation. A serial signal in which the information is contained in the width of a pulse of a

constant-frequency signal. By using the timer-compare features, a TMS370 device can output a PWM signal with

a constant-duty cycle without any program intervention.

EDSTRG44PLCC Datasheet(PDF) 42 Page - Texas Instruments

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