Preliminary Technical Data

AD9216

Rev. PrD

Page 9 of 20

6/15/2004

Table 7. Pin Function Descriptions

Pin

Number

Mnemonic

Description

2

VIN+_A

Analog Input Pin (+) for Channel A

3

VIN–_A

Analog Input Pin (- ) for Channel A

15

VIN+_B

Analog Input Pin (+) for Channel B

14

VIN- _B

Analog Input Pin (- ) for Channel B

6

REFT_A

Differential Reference (+) for Channel A

7

REFB_A

Differential Reference (- ) for Channel A

11

REFT_B

Differential Reference (+) for Channel B

10

REFB_B

Differential Reference (- ) for Channel B

8

VREF

Voltage Reference Input/Output

9

SENSE

Reference Mode Selection

18

CLK_B

Clock Input Pin for Channel B

63

CLK_A

Clock Input Pin for Channel A

19

DCS

Enable Duty Cycle Stabilizer (DCS) Mode ( Tie to AVDD to enable)

20

DFS

Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement)

21

PDWN_B

Power-Down Function Selection for Channel B (Active High)

60

PDWN_A

Power-Down Function Selection for Channel A (Active High)

22

OEB_B

Output Enable Bit for Channel B (Low Setting Enables Channel B Output Data Bus)

59

OEB_A

Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus)

46–51, 54-

57

D0_A (LSB)-D9_A

(MSB)

Channel A Data Output Bits

27, 30-38

D0_B (LSB) –D9_B

(MSB)

Channel B Data Output Bits

39

OTR_B

Out-of-Range Indicator for Channel B

58

OTR_A

Out-of-Range Indicator for Channel A

62

SHARED_REF

Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared

Reference Mode)

61

MUX_SELECT

Data Multiplexed Mode. (See description for how to enable; high setting disables output data

Multiplexed mode)

5, 12, 17,

64

AVDD

Analog Power Supply

1, 4, 13, 16

AGND

Analog Ground

28, 40, 53

DRGND

Digital Output Ground

29, 41, 52

DRVDD

Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.

Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF

23-26, 42-

45

DNC

Do Not Connect Pins. Should be left floating.