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TSB43AB21AI Datasheet(PDF) 39 Page - Texas Instruments |
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TSB43AB21AI Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 116 page  3–17 3.23 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3–21 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Miscellaneous configuration Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Miscellaneous configuration Type R/W R R/W R R R/W R R R R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Miscellaneous configuration Offset: F0h Type: Read/Write, Read-Only Default: 0000 0000h Table 3–21. Miscellaneous Configuration Register BIT FIELD NAME TYPE DESCRIPTION 31–16 RSVD R Reserved. Bits 31–16 return 0s when read. 15 PME_D3COLD R/W PCI_PME support from D3cold. This bit programs bit 15 (PME_D3COLD) in the power management capabilities register at offset 46h in the PCI configuration space (see Section 3.19, Power Management Capabilities Register). 14–5 RSVD R Reserved. Bits 14–5 return 0s when read. 4 DIS_TGT_ABT R/W Bit 4 defaults to 0, which provides iOHCI-Lynx compatible target abort signaling. When this bit is set to 1, it enables the no-target-abort mode, in which the TSB43AB21A device returns indeterminate data instead of signaling target abort. The TSB43AB21A LLC is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the link that are not active because the SCLK is disabled, a target abort is issued by the link. On some systems, this can cause a problem resulting in a fatal system error. Enabling this bit allows the link to respond to these types of requests by returning FFh. It is recommended that this bit be set to 1. 3 GP2IIC R/W When bit 3 is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA, respectively. The GPIO3 and GPIO2 terminals are also placed in the high-impedance state. 2 DISABLE_SCLKGATE R/W When bit 2 is set to 1, the internal SCLK runs identically with the chip input. This is a test feature only and must be cleared to 0 (all applications). 1 DISABLE_PCIGATE R/W When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature only and must be cleared to 0 (all applications). 0 KEEP_PCLK R/W When bit 0 is set to 1, the PCI clock is always kept running through the PCI_CLKRUN protocol. When this bit is cleared, the PCI clock can be stopped using PCI_CLKRUN. |
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