TSB43AB21AI datasheet(63/116 Pages) TI

63 / 116 page

4–21

Table 4–16. Interrupt Mask Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

cycle64Seconds

RSC

When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this 64-second-cycle interrupt mask enables

interrupt generation.

cycleSynch

RSC

When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this isochronous-cycle interrupt mask enables

interrupt generation.

phy

RSC

When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

Interrupt Event Register) are set to 1, this PHY-status-transfer interrupt mask enables interrupt

generation.

regAccessFail

RSC

When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this register-access-failed interrupt mask enables

interrupt generation.

busReset

RSC

When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this bus-reset interrupt mask enables interrupt

generation.

selfIDcomplete

RSC

When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this self-ID-complete interrupt mask enables

interrupt generation.

selfIDcomplete2

RSC

When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this second-self-ID-complete interrupt mask

enables interrupt generation.

14–10

RSVD

Reserved. Bits 14–10 return 0s when read.

lockRespErr

RSC

When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this lock-response-error interrupt mask enables

interrupt generation.

postedWriteErr

RSC

When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this posted-write-error interrupt mask enables

interrupt generation.

isochRx

RSC

When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this isochronous-receive-DMA interrupt mask

enables interrupt generation.

isochTx

RSC

When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this isochronous-transmit-DMA interrupt mask

enables interrupt generation.

RSPkt

RSC

When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

Interrupt Event Register) are set to 1, this receive-response-packet interrupt mask enables interrupt

generation.

RQPkt

RSC

When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

Interrupt Event Register) are set to 1, this receive-request-packet interrupt mask enables interrupt

generation.

ARRS

RSC

When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

Interrupt Event Register) are set to 1, this asynchronous-receive-response-DMA interrupt mask

enables interrupt generation.

ARRQ

RSC

When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

Interrupt Event Register) are set to 1, this asynchronous-receive-request-DMA interrupt mask enables

interrupt generation.

respTxComplete

RSC

When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this response-transmit-complete interrupt mask

enables interrupt generation.

reqTxComplete

RSC

When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this request-transmit-complete interrupt mask

enables interrupt generation.

TSB43AB21AI Datasheet(PDF) 63 Page - Texas Instruments

TSB43AB21AI Datasheet(HTML) 63 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL