M69AW024BE datasheet(8/25 Pages) STMICROELECTRONICS

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M69AW024BE

8/25

OPERATION

Operational modes are determined by device con-

trol inputs W, E1, E2, LB and UB as summarized

in the Operating Modes table (see Table 2.).

Power On Sequence

Because

the

internal

control

logic

the

M69AW024BE needs to be initialized, the follow-

ing power-on procedure must be followed before

the memory is used:

–

Apply power and wait for VCC to stabilize

–Wait tCHEL while driving both Chip Enable

signals (E1 and E2) High

–

Activate the memory by driving Chip

Enable (E1) Low.

Read Mode

The device is in Read mode when:

–

Write Enable (W) is High and

–

Output Enable (G) Low and

–

the two Chip Enable signals are asserted

(E1 is Low, and E2 is High).

The time taken to enter Read mode (tELQV, tGLQV

or tBLQV) depends on which of the above signals

was the last to reach the appropriate level.

Data out (DQ15-DQ0) may be indeterminate

during tELQX, tGLQX and tBLQX, but data will always

be valid during tAVQV.

Write Mode

The device is in Write mode when

–

Write Enable (W) is Low and

–

Chip Enable (E1) is Low and

–

the two Chip Enable signals are asserted

(E1 is Low, and E2 is High)

–

one of Upper Byte Enable (UB) or Lower

Byte Enable (LB) is Low, while the other is

High.

The Write cycle begins just after the event (the fall-

ing edge) that causes the last of these conditions

to become true (tAVWL, tAVEL or tAVBL).

The Write cycle is terminated by the earlier of a ris-

ing edge on Write Enable (W) or Chip Enable (E1).

If the device is in Write mode (Chip Enable (E1) is

Low, Output Enable (G) is Low, Upper Byte En-

able (UB) or Lower Byte Enable (LB) is Low), then

Write Enable (W) will return the outputs to high im-

pedance within tWHDZ of its falling edge. Care

must be taken to avoid bus contention in this type

of operation. Data input must be valid for tDVWH

before the rising edge of Write Enable (W), or for

tDVEH before the rising edge of Chip Enable (E1),

whichever occurs first, and remain valid for tBHDZ,

tWHDZ, tEHDZ.

Standby Mode

The device is in Standby mode when:

–

Chip Enable (E1)is High and

–

Chip Enable (E2) is High.

The input/output buffers and the decoding/control

logic are switched off, but the dynamic array con-

tinues to be refreshed. In this mode, the memory

current consumption, ISB, is reduced, and the data

remains valid.

Deep Power-down Mode

The device is in Deep Power-down mode when:

–

Chip Enable (E2 is Low).

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