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DS3252 Datasheet(PDF) 54 Page - Maxim Integrated Products |
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DS3252 Datasheet(HTML) 54 Page - Maxim Integrated Products |
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54 / 71 page  DS3251/DS3252/DS3253/DS3254 54 of 71 Table 17-I. SPI Interface Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 17-5) PARAMETER (Note 1) SYMBOL MIN TYP MAX UNITS SCLK Frequency fBUS 10 MHz SCLK Cycle Time tCYC 100 ns CS Setup to First SCLK Edge tSUC 15 ns CS Hold time After Last SCLK Edge tHDC 15 ns SCLK High Time tCLKH 50 ns SCLK Low Time tCLKL 50 ns SDI Data Setup Time tSUI 5 ns SDI Data Hold Time tHDI 15 ns SDO Enable Time (High-Impedance to Output Active) tEN 0 ns SDO Disable Time (Output Active to High-Impedance) tDIS 25 ns SDO Data Valid Time tDV 40 ns SDO Data Hold Time After Update SCLK Edge tHDO 5 ns Note 1: All timing is specified with 100pF load on all SPI pins. Figure 17-5. SPI Interface Timing Diagram CS SCLK, CPOL=0 SCLK, CPOL=1 t SUI t HDI SDI t CYC t SUC t CLKH t CLKL t CLKL t CLKH t HDC SDO t EN t DV t HDO t DIS CPHA = 0 CPHA = 1 CS SCLK, CPOL=0 SCLK, CPOL=1 t CYC t SUC t CLKH t CLKL t CLKL t HDC t SUI t HDI SDI SDO t EN t DV t HDO t DIS t CLKH |
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