(Preliminary)

PL580-30

38MHz-640MHz Low Phase Noise VCXO

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 2

OUTPUT ENABLE LOGICAL LEVELS

(Pad #25)

OUTSEL1^

(Pad #18)

Selected Output

0

0

LVDS

0

1

PECL (Default)

1

0

High Drive CMOS

1

1

Standard Drive CMOS

Note: For bonding convenience, ‘OUTSEL0’ incorporates an internal pull down resistor while ‘OUTSEL1’ incorporates an internal pull up resistor.

OUTPUT SELECTION AND ENABLE

OE_SEL^

(Pad #9)

OE_CTRL

(Pad #30)

State

0 (Default)

Output enabled

0

1

Tri-state

0

Tri-state

1 (Default)

1 (Default)

Output enabled

Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”,

Pad #30: Logical states defined by PECL levels if OE_SELECT is “0”

Logical states defined by CMOS levels if OE_SELECT is “1”

FREQUENCY SELECTION TABLE

SEL2

SEL1

SEL0

Selected Multiplier/Output Frequency

0

0

0

VCO Max*

0

0

1

VCO Min*

0

1

0

Reserved

0

1

1

Reserved

1

0

0

Fin x 2

1

0

1

Fin x 8

1

1

0

Fin x 16

1

1

1

Fin x 4

All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0.

* Special Test Modes to help selecting the inductor value for the target output frequency.