(Preliminary)

PL580-30

38MHz-640MHz Low Phase Noise VCXO

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 1

FEATURES

• Less than 0.4ps RMS (12KHz-20MHz) phase

• Low phase noise output (@ 1MHz frequency

offset

∗ -140dBc/Hz for 311.04MHz,

∗ -131dBC/Hz for 622.08MHz

• 19MHz-40MHz crystal input.

• 38MHz-640MHz output.

• Selectable PECL, LVDS, or CMOS outputs.

• No external varicap required.

• Output Enable selector.

• Wide pull range (+/-200ppm).

• 3.3V operation.

• Available in 3x3 QFN or 16-pin TSSOP

packages.

DESCRIPTION

The PL580-30 is a monolithic low jitter and low

phase noise VCXO, capable of 0.4ps RMS phase

jitter and PECL, LVDS, or CMOS outputs, covering a

wide frequency output range up to 640MHz. It allows

the control of the output frequency with an input

voltage (VCON), using a low cost crystal.

The PL580-30 is designed to address the demanding

requirements of high performance applications such

as SONET, GPS, XDSL, etc.

BLOCK DIAGRAM

DIE CONFIGURATION

Note1: ^ Denotes internal pull up resistor.

DIE SPECIFICATIONS

Name

Value

Size

62 x 65 mil

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

10 mil

18

19

20

21

23

25

7

13

10

26

29

31

Y

X

(0,0)

(1550,1475)

65 mil

24

22

17

16

15

14

12

11

9

8

6

12345

27

28

30

OE_SEL^

GNDBUF

CMOS

LVDSB

PECLB

VDDBUF

VDDBUF

PECL

LVDS

XIN

XOUT

DNC

SEL2

OE_CTRL

VCON

Die ID:

2222-22A

C502A

Phase

Detector

Charge

Pump

Loop

Filter

VCO

VCO

Divider

XTAL

OSC

QBAR

OE

XIN

XOUT

Q

VCON

VARICAP

+

Performance Tuner

Output

Divider

(1,2,4,8)