MAX187 Evaluation System/Evaluation Kit

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9

__________________TMS320 Interface

The TMS320 subdirectory of the program disk contains

a demonstration program that interfaces the MAX187 to

Texas Instruments’ TMS320C3X Evaluation Module

(EVM), as shown in Figure 3. This demonstration

requires the additional software included with the

TMS320C3X EVM board, and is provided for the conve-

nience of programmers who are already familiar with

Texas Instruments’ TMS320 family of digital signal

processors. To connect the MAX187 EV kit to the

TMS320C3X EVM, install a 2 x 5 pin ribbon-cable head-

er in the prototype area and wire it in accordance with

Table 7. The SHDN pin should be tied to 5V for normal

operation.

The demo software configures the TMS320C30 so that

FSR1 and DR1 are inputs, and CLKR1 and XF1 are out-

puts. The software uses the XF1 output to start a con-

version. The XF1 pulse drives the MAX187 chip-select

input. The CLKR1 output provides the serial clock to

the MAX187. Data output from the MAX187 is received

on the DR1 input. The FSR1 frame-start signal is also

tied to the data output, so the start bit from the MAX187

marks the beginning of the serial frame.

To read the MAX187, the software drives the XF1 out-

put low, then waits 8.5µs (the maximum conversion

time). It then enables the serial receive clock. The

MAX187 sends its start bit, followed by the serial data.

The demo software polls the serial receiver until a com-

plete frame has been received. Since only 12 of the 16

bits received are significant, the demo software right-

justifies the significant bits and removes the start bit,

then writes the 12-bit word to the TMS320C3XEVM’s

host data port.

For the complete ribbon-cable pinout, consult the

TMS320C3X Evaluation Module Technical Reference

that came with your TMS320C3X EVM.

I/O

I/O

SCK

MISO

68HC11

MAX187

SHDN

CS

10k

+5V

SCLK

DOUT

SS

Figure 3. SPI Interface Schematic

Figure 4. MAX187 to SPI Interface Timing (CPOL = 0, CPHA = 0)

5

4

3

2

1

START BIT

CS

D11

D10

SCLK

(SCK)

DOUT

(MISO)

1

MAX187 CONVERSION TIME: 8.5µs MAX

NOTE: TIMING DIAGRAM NOT DRAWN TO SCALE

2

SPI SETUP TIME: 100ns MIN

3

SPI HOLD TIME: 100ns MIN

4

MAX187 SCK TO DOUT DELAY: 150ns MAX

5

SCLK PERIOD: (150ns + 100ns) (2) = 500ns

ACTUAL PERIOD =

= 1000ns

1

1MHz