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DA7400 Datasheet(PDF) 39 Page - Dialog Semiconductor |
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DA7400 Datasheet(HTML) 39 Page - Dialog Semiconductor |
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39 / 135 page  DA7400 High Performance Stereo Codec Final Datasheet Revision 3.0 03-Jul-2020 CFR0011-120-00 39 of 135 © 2020 Dialog Semiconductor 9.3 Block Diagram MICL MICR HPL HPR DMI C_A0 DMI C_A1 PCM_DATA_OUT [2] PCM_DATA_IN [1] PCM_DATA_O UT [1] PCM_DATA_OUT [3:6] PCM_DATA_IN [3:6] PCM_DATA_IN [2] Ip0 Ip1 Ip2 Ip3 Ip4 Ip5 Ip6 Ip7 Ip8 Ip9 Op0 Op1 Op2 Op3 Op4 to 7 DMI C_B0 DMI C_B1 Figure 16: APU Signal Path Diagram 9.4 Block Architecture The APU block contains the following sub-blocks: ■ DSP, see Section 9.5 ■ SRAM, see Section 9.6 The APU contains two banks of SRAM program memory, PROG-0 and PROG-1, to support seamless switching between DSP programs. The active memory bank is selected using the system sequencer, see Section 7. The system sequencer automatically ramps up and down the audio paths to ensure switching between DSP programs is done in a pop-and-click free manner. The DSP sub-block operates at the incoming DAI sample rate, or at 192 kHz to minimize latency if required. |
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