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DA7400 Datasheet(PDF) 37 Page - Dialog Semiconductor |
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DA7400 Datasheet(HTML) 37 Page - Dialog Semiconductor |
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37 / 135 page ![]() DA7400 High Performance Stereo Codec Final Datasheet Revision 3.0 03-Jul-2020 CFR0011-120-00 37 of 135 © 2020 Dialog Semiconductor 8.6 Clock Generator The clock generator is responsible for generating all the required clocks. The input to the clock generator is the PLL output if the PLL is locked; otherwise the internal oscillator is used. All outputs have independent clock gates to minimize power consumption when not in use. sys_clk 0 1 lock Clock Generator clk_sequencer pll_out clk_adc clk_dac clk_dsp clk_dmic_ab clk_dai clk_in_filter clk_out_filter clk_hp_cp clk_i2c clk_sram clk_siggen Figure 14: Clock Generator Block Diagram |
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