DA7400 datasheet(8/135 Pages) DIALOG

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DA7400

High Performance Stereo Codec

Final

Datasheet

Revision 3.0

03-Jul-2020

CFR0011-120-00

8 of 135

Figure 24: Slave Mode ........................................................................................................................ 48

Figure 25: I2S Format .......................................................................................................................... 49

Figure 26: DSP Format........................................................................................................................ 49

Figure 27: Left-Justified Format .......................................................................................................... 49

Figure 28: Right-Justified Format ........................................................................................................ 50

Figure 29: TDM Configuration ............................................................................................................. 50

Figure 30: Two Devices in LJF with TDM Mode Active....................................................................... 51

Figure 31: One Device in DSP Mode with Offset from TDM Mode ..................................................... 52

Figure 32: SRC Block Diagram ........................................................................................................... 52

Figure 33: DMIC Interface Block Diagram........................................................................................... 53

Figure 34: DMIC Interface Timing and Sampling Points ..................................................................... 54

Figure 35: DA7400 DMIC Interface Router ......................................................................................... 54

Figure 36: Signal Generator Block Diagram........................................................................................ 55

Figure 37: Set Switching...................................................................................................................... 56

Figure 38: Configuring a New Set ....................................................................................................... 57

Figure 39: Gain Change Thresholds and Attack, Hold, and Decay Times ......................................... 62

Figure 40: WLCSP32 Package Outline Diagram .............................................................................. 131

Figure 41: DA7400 External Components Diagram .......................................................................... 133

Figure 42: DA7400 WLCSP PCB Layout .......................................................................................... 134

Tables

Table 1: Pin Description ...................................................................................................................... 15

Table 2: Pin Type Definition ................................................................................................................ 16

Table 3: Absolute Maximum Ratings................................................................................................... 17

Table 4: Recommended Operating Conditions ................................................................................... 17

Table 5: Bandgap ................................................................................................................................ 18

Table 6: VREF ..................................................................................................................................... 18

Table 7: LDO ....................................................................................................................................... 18

Table 8: Input Path .............................................................................................................................. 19

Table 9: Input Filters ............................................................................................................................ 19

Table 10: Automatic Level Control ...................................................................................................... 20

Table 11: Microphone Bias.................................................................................................................. 21

Table 12: Output Path ......................................................................................................................... 21

Table 13: Output Filters ....................................................................................................................... 22

Table 14: Phase-Locked Loop ............................................................................................................ 23

Table 15: Digital Audio Interface ......................................................................................................... 24

Table 16: I2C ....................................................................................................................................... 25

Table 17: System Latency ................................................................................................................... 26

Table 18: DA7400 System Power Consumption ................................................................................. 26

Table 19: PLL Output Clock Frequencies ........................................................................................... 36

Table 20: APU Inputs .......................................................................................................................... 40

Table 21: APU Outputs........................................................................................................................ 40

Table 22: Memory Map........................................................................................................................ 41

Table 23: DAI Pins and Signals........................................................................................................... 48

Table 24: Register Map ....................................................................................................................... 68

Table 25: SEQ_CHIP_ID_HI (0x0200) ................................................................................................ 81

Table 26: SEQ_CHIP_ID_LO (0x0201)............................................................................................... 81

Table 27: SEQ_CHIP_VAR (0x0202).................................................................................................. 81

Table 28: SEQ_CHIP_REV (0x0203).................................................................................................. 81

Table 29: SEQ_INPUT_PATH_SET0 (0x0206) .................................................................................. 81

Table 30: SEQ_OUTPUT_PATH_SET0 (0x0207) .............................................................................. 82

Table 31: SEQ_DSP_CONFIG_SET0 (0x0208) ................................................................................. 82

Table 32: SEQ_PERF_MODE_SET0 (0x020A).................................................................................. 83

Table 33: SEQ_MICBIAS_CONFIG_SET0 (0x020B) ......................................................................... 83

Table 34: SEQ_PCM_CONFIG_SET0 (0x020C) ................................................................................ 83

Table 35: SEQ_APPLY_CONFIG_SET0 (0x020D) ............................................................................ 83

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