DA9131 datasheet(30/56 Pages) DIALOG

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DA9131

High-Performance, Dual-Channel DC-DC Converter for

Mobile and Portable Applications

Datasheet

Revision 2.0

11-Aug-2021

CFR0011-120-00

30 of 56

SCL

SDA

Figure 16: I2C START and STOP Condition Timing

The I2C bus is monitored for a valid slave address whenever the interface is enabled. It responds

immediately when it receives its own slave address. The acknowledge is done by pulling the SDA

line low during the following clock cycle (white blocks marked with A in Figure 17 and Figure 18).

The protocol for a register write from master to slave consists of a START condition, a slave address

with read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a

STOP condition. DA9131 responds to all bytes with acknowledge (A), see Figure 17.

SLAVEadr

REGadr

DATA

S = START condition

A = Acknowledge (low)

P = STOP condition

W = Write (low)

Master to Slave

Slave to Master

7-bits

1-bit

8-bits

Figure 17: I2C Byte Write (SDA Line)

When the host reads data from a register it first has to write to DA9131 with the target register

address and then read from DA9131 with a repeated START, or alternatively a second START,

condition. After receiving the data, the host sends no acknowledge (A*) and terminates the

transmission with a STOP condition, see Figure 18.

SLAVEadr W

REGadr

SLAVEadr

S = START condition

A = Acknowledge (low)

Sr = Repeated START condition

* = No Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

7-bits

1-bit

8-bits

7-bits

DATA

1-bit

8-bits

SLAVEadr

7-bits

DATA

1-bit

8-bits

Slave to Master

SLAVEadr W

REGadr

7-bits

1-bit

8-bits

Figure 18: I2C Byte Read (SDA Line) Examples

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