LAN9255

DS00003646B-page 8

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2020-2021 Microchip Technology Inc.

4.0

PIN CONFIGURATION

This section provides pin assignment information for the LAN9255. Pin descriptions for the various LAN9253 and SAM

E53J functions should be referenced in their respective data sheets, as detailed in Section 1.1, References.

4.1

Pin Assignments

FIGURE 4-1:

PIN ASSIGNMENTS (TOP VIEW)

Note:

When a “

#” is used at the end of the signal name, it indicates that the signal is active low. For example,

RST# indicates that the reset signal is active low. Configuration straps are identified by an underlined sym-

bol name.

121

122

123

124

125

127

128

126

113

114

115

116

117

118

119

120

105

106

107

108

109

110

111

112

97

98

99

100

101

102

103

104

LAN9255

128-TQFP

(Top View)

VSS

Connect exposed pad to ground with a via field

VDDIO_S

PB22

PB23

D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK

D5/AD5/OUTVALID/SCS#

VDD33TXRX1

TXNA

TXPA

RXNA

RXPA

PA27

RESETN_E53

VDDCORE

VDD12TX1

RBIAS

VDD33BIAS

VDD12TX2

VSW

RXPB

RXNB

VDDIO_S

TXPB

TXNB

PA30

PA31

PB30

PB31

VDD33TXRX2

PB00

PB01

PB02

OSCI

PA15

PA14

PA13

PA12

VDDIO_J

RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3

WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2

A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/EE_EMUL_ALELO_POL/MII_LINKPOL/LEDPOL2

CS/DIGIO13/GPI13/GPO13/MII_RXD1

A4/BE1/DIGIO12/GPI12/GPO12/MII_RXD0

A3/BE0/DIGIO11/GPI11/GPO11/MII_RXDV

A1/ALELO/OE_EXT/MII_CLK25//EE_EMUL_SPI2

VDDCR

D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN

D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0/100FD_A

D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1/100FD_B

NC

PB15

PB14

VDDIO_J

PB13

PB12

PB11

D9/AD9/LATCH_IN/SCK

PB10

SYNC1/LATCH1/PME

D0/AD0/WD_STATE/SI/SIO0

VDDIOB

PA11

PA10

PA09

PA08