2

EVDP610

In this manner the user can easily set pulse width, dead

time, resolution, among other functions such as dividing

the clock signal.

2.2 IXDP610 IC

The IXDP610 chip, labeled U1 on the evaluation board,

generates two complementary non-overlapping, pulse

width modulated signals for direct digital control of a

switching power bridge.

2.2.1 Dead Time

The PWM waveform generated by the IXDP610 results

from comparing the output of the Pulse Width counter to

the number stored in the Pulse Width Latch. A program-

mable “dead-time” (defined as t

into the PWM waveform. The Dead-Time Logic disables

both outputs on each transition of the comparator output

for the required dead-time interval. This feature is difficult

to duplicate in equivalent analog system.

For example, in a half bridge system the dead time can

prevent two transistors being on at the same time. If both

transistors are on for a short period of time, they could

effectively short the voltage supple to ground, which is an

undesirable situation.

2.2.2 Lock Bit

Setting the lock bit of the IXDP610 prevents all writes to

the control latch except for the Stop bit. This locking

feature prevents modification of the control latch due to

software error, preventing damage to the system being

controlled by the IXDP610. This prevents changing of the

dead-time, clock divide, and resolution settings.

2.2.3 Clock Divide Bit

This feature allows the IXDP610 to divide the input clock

by one or divided by two.

2.2.4 Resolution

The IXDP610 can run in two resolution modes, 8-bit and

7-bit. Choosing 7-bit resolution doubles the achievable

PWM base frequency at the expense of decreased duty

cycle resolution. With the combination of the Divide bit

(labeled Clock Divide on the GUI) and the resolution bit,

running after establishing communication. This

assures that both the board and the software are

initialized into the same states to avoid confusion.

2. Make sure that the board is in 8 bit resolution mode

by checking the resolution button (8 bit resolution is

the board's default state). Flip the switch in the

Pulse Settings area so that the pulse width test box

is now no longer dimmed. Enter a number into this

text box between 0 – 255. The duty cycle textbox

will change accordingly although it will remain

dimmed until the switch is toggled, ie: if you enter a

128, the duty cycle will read 50%.

2.0 GENERAL DESCRIPTION AND THEORY OF

OPERATION

For circuit design information, refer to the EVDP610

schematic and PCB layout drawing in Figures 7 and 8.

2.1 Serial Communications

The RS-232 communications interface allow the

EVDP610 to communicate and respond to commands

through a serial port. The serial bus operates at 9600

baud and is buffered by an RS232 driver before reaching

the microprocessor. For more specific information on

the serial protocol please see Section 4.

To communicate with and control the EVDP610 Board, a

null modem cable (included) must be connected from a

PC’s serial port to the male DB9 connector on the board.

For user reference a pin out of the cable is shown in

Figure 3. Once the correct communications port is

selected, the user can run all of the features of the

IXDP610 chip from the GUI.

The GUI software allows the user to set all functions

provided on the IXDP610 with the simple click of a button

or writing into a text box.

Female DB9

(computer)

Female DB9

(EVDP610 board)

Description

Pin 2

Pin 3

TX

Pin 3

Pin 2

RX

Pin 5

Pin 5

GND

Figure 3 - Null Modem Cable Pin-Out

Figure 4: Output Waveform Displaying Dead-Time