MCIMX6DP6AYM2AB datasheet(21/160 Pages) NXP

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Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

4.1.2

Thermal Resistance

NOTE

Per JEDEC JESD51-2, the intent of thermal resistance measurements is

solely for a thermal performance comparison of one package to another in a

standardized environment. This methodology is not meant to and will not

predict the performance of a package in an application-specific

environment.

4.1.2.1

FCPBGA Package Thermal Resistance

Table 5 provides the FCPBGA package thermal resistance data for the lidded package type.

Table 5. FCPBGA Package Thermal Resistance Data (Lidded)

Thermal Parameter

Test Conditions

Symbol

Value

Unit

Junction to Ambient1

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

Single-layer board (1s); natural convection2

2 Per JEDEC JESD51-3 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified

package.

RθJA

°C/W

Four-layer board (2s2p); natural convection2

RθJA

°C/W

Junction to Ambient1

Single-layer board (1s); air flow 200 ft/min3

3 Per JEDEC JESD51-6 with the board horizontal.

RθJMA

°C/W

Four-layer board (2s2p); air flow 200 ft/min4

RθJMA

°C/W

Junction to Board1,4

4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

—RθJB

°C/W

Junction to Case (top)1,5

5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1). The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the

interface layer.

—RθJCtop

°C/W

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