MCIMX6DP6AYM2AB datasheet(64/160 Pages) NXP

64 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

Figure 25. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)

Figure 26. Read Data Latch Cycle Timing Diagram (EDO Mode)

Table 40. Asynchronous Mode Timing Parameters1

Parameter

Symbol

Timing

T = GPMI Clock Cycle

Unit

Min

Max

NF1

NAND_CLE setup time

tCLS

(AS + DS)

× T - 0.12 [see 2,3]ns

NF2

NAND_CLE hold time

tCLH

× T - 0.72 [see 2]ns

NF3

NAND_CEx_B setup time

tCS

(AS + DS + 1)

× T [see 3,2]ns

NF4

NAND_CEx_B hold time

tCH

(DH+1)

× T - 1 [see 2]ns

NF5

NAND_WE_B pulse width

tWP

× T [see 2]ns

NF6

NAND_ALE setup time

tALS

(AS + DS)

× T - 0.49 [see 3,2]ns

NF7

NAND_ALE hold time

tALH

(DH

× T - 0.42 [see 2]ns

NF8

Data setup time

tDS

× T - 0.26 [see 2]ns

NF9

Data hold time

tDH

× T - 1.37 [see 2]ns

NF10

Write cycle time

tWC

(DS + DH)

× T [see 2]ns

NF11

NAND_WE_B hold time

tWH

× T [see 2]ns

NF12

Ready to NAND_RE_B low

tRR4

(AS + 2)

× T [see 3,2]—

NF13

NAND_RE_B pulse width

tRP

× T [see 2]ns

NF14

READ cycle time

tRC

(DS + DH)

× T [see 2]ns

NF15

NAND_RE_B high hold time

tREH

× T [see 2]ns

Data from NF

NF14

NF15

NF17

NF16

NF12

NF13

Data from NF

NF14

NF15

NF17

NF16

NF12

NF13

NAND_DATAxx

MCIMX6DP6AYM2AB Datasheet(PDF) 64 Page - NXP Semiconductors

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