MCIMX6DP6AYM2AB datasheet(13/160 Pages) NXP

13 / 160 page

Modules List

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

LDB

LVDS Display Bridge Connectivity

Peripherals

LVDS Display Bridge is used to connect the IPU (Image Processing Unit)

to External LVDS Display Interface. LDB supports two channels; each

channel has following signals:

• One clock pair

• Four data pairs

Each signal pair contains LVDS special differential pad (PadP, PadM).

MMDC

Multi-Mode DDR

Controller

Connectivity

Peripherals

DDR Controller has the following features:

• Supports 16/32/64-bit DDR3 / DDR3L or LPDDR2

• Supports both dual x32 for LPDDR2 and x64 DDR3 / LPDDR2

configurations (including 2x32 interleaved mode)

• Supports LPDDR2 up to 400 MHz and DDR3 up to 532 MHz

• Supports up to 4 GByte DDR memory space

OCOTP_CTRL OTP Controller

Security

The On-Chip OTP controller (OCOTP_CTRL) provides an interface for

reading, programming, and/or overriding identification and control

information stored in on-chip fuse elements. The module supports

electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also

provides a set of volatile software-accessible signals that can be used for

software control of hardware elements, not requiring non-volatility. The

OCOTP_CTRL provides the primary user-visible mechanism for

interfacing with on-chip fuse elements. Among the uses for the fuses are

unique chip identifiers, mask revision numbers, cryptographic keys, JTAG

secure mode, boot characteristics, and various control signals, requiring

permanent non-volatility.

OCRAM

On-Chip Memory

Controller

Data Path

The On-Chip Memory controller (OCRAM) module is designed as an

interface between system’s AXI bus and internal (on-chip) SRAM memory

module.

In i.MX 6DualPlus/6QuadPlus processors, the OCRAM is used for

controlling the 512 KB multimedia RAM through a 64-bit AXI bus.

OSC 32 kHz

Clocking

Generates 32.768 kHz clock from an external crystal.

PCIe

PCI Express 2.0

Connectivity

Peripherals

The PCIe IP provides PCI Express Gen 2.0 functionality.

Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

MCIMX6DP6AYM2AB Datasheet(PDF) 13 Page - NXP Semiconductors

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