MAX22005 datasheet(21/47 Pages) MAXIM

21 / 47 page

Table 3. SPI Transaction with CRC Disabled

BITS 31:25

BIT 24

BITS 23:0

R/W

24-bit Payload

The MAX22005 implements the CRC-8/MAXIM algorithm with an 0x31 polynomial (x8 + x5 + x4 + x0), the same

polynomial that is used in Maxim’s 1-wire® products. This CRC algorithm uses reflected input and output bytes (i.e., LSB

first instead of MSB first on a byte basis; the byte order of the input sequence is not changed). The initial value is 0x00,

and the output is reported as is without any XOR operation.

This CRC can detect the following types of errors:

● Any odd number of errors anywhere within the 32-bit number

● All double-bit errors anywhere within the 32-bit number

● Any cluster of errors that can be contained within an 8-bit window (1–8 bits incorrect)

● Most large clusters of errors

For write transactions, the CRC is calculated on the 32 bits that precede it, namely the 7-bit register address, 1-bit read

or write control, and the 24-bit payload.

Here are two examples of write operations:

Write 0x00_0F00 to register GEN_CHNL_CTRL: 0x06_000F_0011

Write 0x34_0000 to register CHNL_CMD: 0x40_3400_00A0

For read transactions, the CRC sent by the MAX22005 back to the host is calculated on 32 bits made of the 8-bit header

received from the host (register address and read control) and the 24 bits of payload.

Here are two examples of read operations:

Read the default value from register GEN_CNFG: 0x05_1000_00CB

Read the default value from register DCHNL_STA: 0x43_0000_08AA

CRC is disabled by default. Refer to AN27 for more details.

Watchdog Timer

The MAX22005 features a watchdog timer for additional security of losing communication with the host controller.

The watchdog can be enabled in the GEN_CNFG register (0x02) by setting the TMOUT_EN bit and setting up the

TMOUT_CNFG, and TMOUT_SEL[3:0] bits for a desired interrupt behavior and timeout duration. The interrupt is

asserted on the INT pin and in TMOUT_INT bit in the GEN_INT register (0x07) if the duration between two properly

formatted SPI transactions exceeds the timeout period. A properly formatted transaction is a transaction that has a

minimum of 32 bits (if CRC is disabled) or 40 bits (if CRC is enabled). A properly formatted transaction is always

accounted for at the end of the transaction. Refer to the Register Map descriptions for more information.

Product Tracking

The MAX22005 includes a 32-bit wide unique serial number used for device tracking (SERIAL[32:0] in registers

GEN_PROD and GEN_REV).

In addition, an eight-bit product ID that helps to distinguish different parts of the industrial I/O family (PROD_ID[7:0] in

Table 4. Product ID

BIT 7

Number of output Channels

Number of Input Channels

RTD/TC Support

The MAX22005 can accept up to 12 input channels; the product ID is 0x18.

The revision of the silicon is reflected in the eight-bit revision ID (REV_ID[7:0] in register GEN_REV).

Analog Input ADC

The analog input channels share one high-performance 24-bit delta-sigma analog-to-digital converter (ADC). The data

MAX22005

12-Channel Factory-Calibrated

Configurable Industrial-Analog Input

www.maximintegrated.com

Maxim Integrated | 21

MAX22005 Datasheet(PDF) 21 Page - Maxim Integrated Products

MAX22005 Datasheet(HTML) 21 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL