MPC8548EEC datasheet(46/151 Pages) NXP

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Local Bus

NOTE

PLL bypass mode is required when LBIU frequency is at or below 83 MHz.

When LBIU operates above 83 MHz, LBIU PLL is recommended to be

enabled.

Figure 23 through Figure 28 show the local bus signals.

Figure 23. Local Bus Signals (PLL Enabled)

This table describes the timing parameters of the local bus interface at BVDD = 3.3 V with PLL disabled.

Table 42. Local Bus Timing Parameters—PLL Bypassed

Parameter

Symbol1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

—

Local bus duty cycle

tLBKH/tLBK

—

Internal launch/capture clock to LCLK delay

tLBKHKT

2.3

4.4

Input setup to local bus clock (except LGTA/LUPWAIT)

tLBIVKH1

6.2

—

4, 5

LGTA/LUPWAIT input setup to local bus clock

tLBIVKL2

6.1

—

4, 5

Input hold from local bus clock (except LGTA/LUPWAIT)

tLBIXKH1

–1.8

—

4, 5

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKHOV1

tLBKHOV2

tLBKHOV3

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

Output (Address) Signal:

LAD[0:31]

LALE

tLBIXKH1

tLBIVKH1

tLBIVKH2

tLBIXKH2

tLBKHOX1

tLBKHOZ1

tLBKHOX2

tLBKHOZ2

Input Signal:

LGTA

tLBOTOT

tLBKHOZ2

tLBKHOX2

tLBKHOV4

LUPWAIT

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