MPC8548EEC datasheet(48/151 Pages) NXP

Part #	MPC8548EEC

Description	MPC8548E PowerQUICC III Integrated Processor Hardware Specifications

PDF	151 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Local Bus

Figure 24. Local Bus Signals (PLL Bypass Mode)

NOTE

In PLL bypass mode, LCLK[n] is the inverted version of the internal clock

with the delay of t

LBKHKT. In this mode, signals are launched at the rising edge

of the internal clock and are captured at falling edge of the internal clock

with the exception of LGTA/LUPWAIT (which is captured on the rising

edge of the internal clock).

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKLOV2

LCLK[n]

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

LALE

tLBIXKH1

Input Signal:

LGTA

Output (Address) Signal:

LAD[0:31]

tLBIVKH1

tLBIXKL2

tLBIVKL2

tLBKLOX1

tLBKLOZ2

tLBOTOT

Internal Launch/Capture Clock

tLBKLOX2

tLBKLOV1

tLBKLOV3

tLBKLOZ1

tLBKHKT

tLBKLOV4

LUPWAIT

MPC8548EEC Datasheet(PDF) 48 Page - NXP Semiconductors

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