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DC9010B Datasheet(PDF) 22 Page - Linear Technology |
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DC9010B Datasheet(HTML) 22 Page - Linear Technology |
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22 / 43 page ![]() IPCS (SPI Slave) For parts that are not locked, the Eterna Flash emulator uses the IPCS bus in conjunction with the RESETn and FLASH_P_ENn signals. To enter the flash emulator, assert both RESETn and FLASH_P_ENn (both low), and then after 10ms, the host communicate with the emulator via the bus, at a maximum rate of 3.33 MHz. Operation is controlled by a protocol mastered externally. Commands starts with the falling edge of IPCS_SSn followed by an appropriate 8-bit instruction, listed below, followed by appropriate address and/or data. While IPCS_SSn is low, data from IPCS_MOSI is clocked from the master on the rising edge of IPCS_SCK, MSB first. As appropriate, status and read data from the device is clocked out on IPCS_MISO on the falling edge of IPCS_SCK, for sampling by the master on the rising edge. 22 ETERNA ™ SERIAL PROGRAMMER GUIDE |
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