11 Layout

11.1 Layout Guidelines

For best performance, all traces must be as short as possible. To be most effective, the input and output

capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have

on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects.

11.2 Layout Example

ON

VIN

FLT

VOUT

GND

ILIM

To GPIO To GPIO

Via to VIN

R

ILIM

R

FLT

Via to GND

Figure 11-1. TPS22950 Layout Example

TPS22950

SLVSFJ2 – DECEMBER 2020

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