LT4295 datasheet(37/50 Pages) AD

37 / 50 page

LTC9101-1/

LTC9102/LTC9103

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

initial values are as specified in the LTC9101-1 Software

Interface. These initial values are subject to the state of

pins, such as the AUTO and 4PVALID pins. Register map

default configurations may be stored during manufactur-

ing bring up or field-updated via configuration package

download and will be auto-loaded at boot.

In addition to configuring register map initial values, con-

figuration packages enable port definition as either 2-pair

or 4-pair ports. Ports are configured as 2-pair or 4-pair at

the quad level (groups of 4 ports).

Contact ADI applications support for assistance in gener-

ating custom configuration packages. Configuration pack-

ages are downloaded using normal code download mech-

anisms. Package headers ensure configuration packages

are identified and stored in the appropriate flash partition.

If a stored configuration is utilized, the state of the AUTO,

CFG[0], PWRMD[1:0] and 4PVALID pins can be overwrit-

ten by a configuration package. CFG[2:1] are still required

to inform the LTC9101-1 how many LTC9102/LTC9103

are attached. AD[3:2] are still required to inform the

LTC9101-1 of the base I2C chip address.

Two identical copies of the configuration image are main-

tained under separate ECC and CRC protection for maxi-

mum data protection.

SERIAL DIGITAL INTERFACE

Overview

The LTC9101-1 communicates with the host using a

standard SMBus/I2C 2-wire interface. The LTC9101-1 is a

slave-only device, and communicates with the host master

using standard SMBus protocols. Interrupts are signaled

to the host via INT. The timing diagrams (Figure 5 through

Figure 9) show typical communication waveforms and

their timing relationships. More information about the

SMBus data protocols can be found at www.smbus.org.

The LTC9101-1 requires both the VDD and VEE supply rails

to be present for the serial interface to function.

A second interpretation is more liberal and allows PDs

which only present valid detection signatures on one pair-

set to be powered on the corresponding pairset, regard-

less of the detection result on the other pairset. To disable

a port’s 4-Pair Valid mode, set 4PVALID high or clear the

port’s 4-Pair Valid configuration register. With 4-Pair Valid

mode disabled, a port will power a pairset with a valid

signature regardless of the valid or invalid signature on

the other pairset. See Table 15.

Table 15. 4-Pair Valid Disabled

PAIRSET

DETECTION

SIGNATURE

ALTERNATIVE A

INVALID

ALTERNATIVE A

VALID

ALTERNATIVE B

INVALID

Port Unpowered

Power A

ALTERNATIVE B

VALID

Power B

Power A and B

Any PD powered with a valid detection signature on one

pairset is treated as a dual-signature PD with one pairset

unpowered.

Code Download

LTC9101-1 firmware is field-upgradable by downloading

and executing firmware images.

Contact Analog Devices for code download procedures

and firmware images.

Firmware images are stored in a dedicated flash partition.

A fully-compliant IEEE 802.3at/bt firmware image is pre-

configured on the LTC9101-1. The firmware image may

be overwritten by the user.

Two complete copies of firmware images are maintained

under separate ECC and CRC protection for maximum

data protection.

Stored Configurations

Custom I2C register map initial values may optionally be

stored in a dedicated flash partition (configuration pack-

age). When shipped from the factory, the LTC9101-1 con-

tains a default configuration package where register map

LT4295 Datasheet(PDF) 37 Page - Analog Devices

LT4295 Datasheet(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL